RRAM Memory Cell Integration With Reduced Interconnect Step Height
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Solution Overview
Problem
Current integrated circuit devices using resistance-based random access memory, such as RRAM, face challenges in efficiently fabricating memory cells with precise control over resistance switching layers and electrode structures, which affects the reliability and integration of these cells into multi-level interconnects.
Innovation Solution
The fabrication process involves forming a memory structure with a bottom electrode, resistance switching layer, and top electrode over a conductive pad, using a combination of low-grade and high-grade masks to simplify the process, reduce cell step height, and integrate memory cells effectively into multi-level interconnects, while optionally omitting dielectric layers and spacers to enhance integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used for RRAM cells, then resistance switching layers and electrode structures can be formed, but the fabrication process becomes complex and cell step height increases
Solution Approach 1:
The fabrication process is divided into distinct stages: forming conductive features in first interlayer dielectric, depositing second interlayer dielectric, and selectively removing portions. This segmentation allows each stage to be optimized independently, reducing overall process complexity while maintaining precision
Solution Approach 2:
Conductive features are formed in the first interlayer dielectric layer before the second interlayer dielectric is deposited. This preliminary action establishes the electrode structures in advance, simplifying subsequent memory cell formation and reducing process complexity
2Reliability
If conventional fabrication processes are used for RRAM cells, then memory cells can be formed, but cell step height increases affecting integration into multi-level interconnects
Solution Approach 1:
Specific dielectric layers and spacer structures are selectively removed (taken out) from the conventional RRAM fabrication process. This extraction eliminates unnecessary height-contributing elements, reducing cell step height while maintaining the essential memory cell functionality and integration reliability
Solution Approach 2:
The fabrication process parameters are changed by omitting certain deposition and etching steps that would otherwise increase cell height. This parameter modification directly reduces the stationary object dimension (cell step height) while preserving the critical resistance switching functionality
Data Source
AI summary
A method for fabricating an integrated circuit device is provided. The method includes forming an interconnect layer over a substrate, wherein the interconnect layer has a first interlayer dielectric layer, a first conductive feature in a first portion of the first interlayer dielectric layer, and a second conductive feature in a second portion of the first interlayer dielectric layer; depositing a dielectric layer over the interconnect layer; removing a first portion of the dielectric layer over the first conductive feature and the first portion of the first interlayer dielectric layer, and remaining a second portion of the dielectric layer over the second conductive feature and the second portion of the first interlayer dielectric layer; and forming a memory structure over the first conductive feature.