RRAM Computing-in-Memory Circuit for Neural Network Convolution
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Solution Overview
Problem
Existing RRAM array-based neural networks have low recognition accuracy and are limited to fully connected layers, failing to utilize the full potential of in-memory computing architectures.
Innovation Solution
A computing-in-memory circuit that includes a RRAM array and a peripheral circuit, capable of storing and processing multiple convolution kernels, allowing for convolution operations in neural networks by representing convolution kernel elements in multiple bits, thereby enhancing recognition accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If binary neural network is deployed on RRAM array, then device complexity is reduced, but recognition accuracy deteriorates
Solution Approach 1:
The patent changes the data representation parameter from binary (1 bit) to multi-bit (2 bits or more) for storing convolution kernel weights in RRAM array. Each memory cell stores multiple bits of weight information, enabling higher precision computation while maintaining the simplicity of RRAM-based implementation. This resolves the contradiction by improving recognition accuracy through increased precision without significantly increasing device complexity.
2Device complexity
If only fully connected layer operation is supported, then device complexity is reduced, but adaptability deteriorates
Solution Approach 1:
The patent designs the RRAM array system to perform multiple neural network operations including convolution, fully connected layer, and activation function operations. By enabling convolution operations with multi-bit precision and supporting various activation functions (ReLU, Sigmoid, Tanh), the system achieves multi-functionality that covers different neural network layers, thereby improving adaptability while maintaining reasonable device complexity.
3Measurement precision
If convolution kernels are stored with multi-bit precision, then recognition accuracy is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent uses 2-bit or multi-bit representation for convolution kernel weights, which provides sufficient precision for accurate computation without requiring extreme manufacturing precision. The multi-bit approach distributes the precision requirement across multiple bits rather than demanding ultra-precise single-value control, making the system feasible with current RRAM manufacturing capabilities while still achieving improved recognition accuracy.
Data Source
AI summary
A computing-in-memory circuit includes a Resistive Random Access Memory (RRAM) array and a peripheral circuit. The RRAM array comprises a plurality of memory cells arranged in an array pattern, and each memory cell is configured to store a data of L bits, L being an integer not less than 2. The peripheral circuit is configured to, in a storage mode, write more than one convolution kernels into the RRAM array, and in a computation mode, input elements that need to be convolved in a pixel matrix into the RRAM array and read a current of each column of memory cells, wherein each column of memory cells stores one convolution kernel correspondingly, and one element of the convolution kernel is stored in one memory cell correspondingly, and one element of the pixel matrix is correspondingly input into a word line that a row of memory cells connect.