RRAM Cell Composite Spacer for Side Wall Verticality
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Solution Overview
Problem
The existing RRAM cell fabrication processes face challenges in achieving smaller, more densely packed cells due to degradation of electrode and resistive layer side walls, leading to performance degradation and lower packing density.
Innovation Solution
The proposed RRAM cell structure includes a first electrode with substantially vertical side walls, a resistive layer with a high dielectric constant, and a capping layer, along with composite spacer regions to protect the side walls and maintain verticality, allowing for a more compact and efficient cell design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional RRAM cell fabrication is used, then manufacturing process is simpler, but electrode and resistive layer side walls degrade leading to lower packing density
Solution Approach 1:
A spacer layer is introduced as an intermediary protective structure between the electrode/resistive layer and the surrounding environment. This spacer layer prevents degradation of the side walls during fabrication processes, maintaining verticality and enabling higher packing density without compromising manufacturing simplicity
Solution Approach 2:
The spacer layer is formed in advance before subsequent fabrication steps that could cause side wall degradation. This preliminary protective action ensures that the electrode and resistive layer maintain their vertical side walls throughout the manufacturing process, achieving both high precision and high packing density
2Productivity
If RRAM cells are made smaller for higher density, then packing density improves, but side wall degradation becomes more severe
Solution Approach 1:
The spacer layer serves as a protective intermediary that becomes increasingly important as cell dimensions are reduced. For smaller cells where side wall degradation has a greater relative impact, the spacer provides critical protection that maintains manufacturing precision even at higher packing densities
3Manufacturing precision
If composite spacer is used to protect side walls, then side wall verticality is maintained, but device complexity increases
Solution Approach 1:
The spacer structure is segmented into multiple layers with different materials, where each layer serves a specific protective function. This segmentation allows for targeted protection of the side walls while maintaining overall structural simplicity and avoiding excessive complexity in the device architecture
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in RRAM cells with improved performance and higher packing density, enabling greater storage capacity in semiconductor devices without significant size increase.
Implementation Method 1
a resistive layer with a high dielectric constant
Data Source
AI summary
A memory cell and method includes a first electrode formed in an opening in a first dielectric layer, the first dielectric layer being formed on a substrate including a metal layer, the opening being configured to allow physical contact between the first electrode and the metal layer, the first electrode having a first width W1 and extending a distance beyond a region defined by the opening, a resistive layer formed on the first electrode and having substantially the first width W1, a capping layer, having a second width W2 less than the first width W1, formed on the resistive layer, a second electrode formed on the capping layer and having substantially the second width W2, a first composite spacer region having at least two different dielectric layers formed on the resistive layer between the first width W1 and the second width W2, and a via coupled to the second electrode.