RRAM Control Circuit Voltage Sequences for Dielectric Breakdown Prevention
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Solution Overview
Problem
The downscaling of memory cells in planar nonvolatile memory devices has reached a limit, necessitating the development of three-dimensional memory devices, where cross-point memory devices offer higher integration by stacking word and bit lines alternately with variable resistance members, but face challenges in efficiently switching and resetting resistance states without causing dielectric breakdown.
Innovation Solution
A resistance random access memory device with a control circuit that applies specific voltage sequences to variable resistance members connected between word and bit lines, switching between low and high resistance states by adjusting voltage polarity and duration to prevent breakdown, using a metal layer and a variable resistance layer with a higher resistivity, and employing a current-limiting layer to manage excessive current flow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high voltage is applied to switch resistance states quickly, then switching speed is improved, but dielectric breakdown risk increases
Solution Approach 1:
The patent applies periodic voltage pulses with different polarities to switch between low and high resistance states. The first voltage pulse (first polarity) switches from high to low resistance state, and the second voltage pulse (second polarity) switches from low to high resistance state. This periodic application of controlled voltage pulses enables high-speed switching while preventing dielectric breakdown through proper pulse width and polarity control.
Solution Approach 2:
The patent changes voltage parameters (magnitude, polarity, pulse width) to optimize switching performance. By adjusting the first voltage to be higher than the second voltage and controlling pulse widths, the system achieves fast switching while maintaining reliability. The variable resistance members respond differently to different voltage parameters, enabling precise control of resistance state transitions.
2Quantity of substance
If three-dimensional cross-point structure is used for higher integration, then memory density is improved, but control precision deteriorates
Solution Approach 1:
The patent segments the memory array into multiple memory cells arranged in a three-dimensional cross-point structure, with word lines and bit lines stacked alternately. Each memory cell contains variable resistance members that can be independently controlled through selective activation of word lines and bit lines. This segmentation enables high integration density while maintaining control precision through the cross-point architecture.
Solution Approach 2:
The patent introduces control circuits as intermediaries to manage voltage application to the three-dimensional memory array. The control circuits selectively apply voltages to specific word lines and bit lines, enabling precise control of individual memory cells or groups of cells. This intermediary control mechanism resolves the challenge of controlling densely packed three-dimensional structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables high-speed and reliable operation of memory cells by efficiently switching resistance states while minimizing the risk of dielectric breakdown, allowing for efficient programming, erasing, and reading of memory cells with improved integration density.
Implementation Method 1
switching resistance states of the variable resistance members from a first state to a second state... when the resistance state of one or more of the variable resistance members... is in the first state
Implementation Method 2
employing a current-limiting layer to manage excessive current flow
Data Source
AI summary
A resistance random access memory device includes a control circuit. The control circuit applies a first voltage between the plurality of second interconnects and one of the first interconnects for a first time when switching resistance states of the variable resistance members from a first state to a second state, and the control circuit applies a second voltage between the plurality of second interconnects and the one of the first interconnects for a second time after applying the first voltage when the resistance state of one or more of the variable resistance members of a plurality of the variable resistance members connected to the one of the first interconnects is in the first state. The second voltage has the same polarity as the first voltage and is lower than the first voltage. The second time is longer than the first time.