RRAM Crossbar Addition Subtraction In-Memory Computing
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Solution Overview
Problem
Addition/subtraction operations cannot be directly deployed in cross-barred RRAM IMC systems, and the non-ideal characteristics of RRAM devices significantly degrade the accuracy of artificial neural networks.
Innovation Solution
A novel RRAM-crossbar hardware architecture is designed to perform addition/subtraction operations in parallel, using a ratio-based scheme that normalizes conductance values, allowing for tolerance against process variations and temperature changes, enabling accurate and robust AI accelerator chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional multiplication-based convolution operations are used in RRAM IMC systems, then computational accuracy is maintained, but hardware resource consumption increases and device complexity increases
Solution Approach 1:
The patent replaces multiplication operations with addition/subtraction operations in RRAM IMC systems. This substitution leverages the natural analog computing capabilities of RRAM devices, where current summation inherently performs addition operations, thereby reducing hardware complexity while maintaining computational accuracy for neural network inference tasks
Solution Approach 2:
The patent changes the computational parameter from multiplication to addition/subtraction operations. By transforming the mathematical operation type, the system achieves the same neural network functionality with simpler hardware requirements, as addition can be naturally implemented through current summation in RRAM crossbar arrays without requiring complex multiplication circuits
2Device complexity
If addition/subtraction operations are used to reduce computational complexity, then device complexity is reduced, but RRAM non-ideal characteristics significantly degrade accuracy
Solution Approach 1:
The patent introduces a calibration mechanism as an intermediary between the RRAM devices and the computation process. This calibration process characterizes and compensates for RRAM non-ideal characteristics such as conductance variability and device mismatch, thereby maintaining high computational accuracy despite the simpler addition-based operations and inherent device non-idealities
Solution Approach 2:
The patent implements feedback through calibration procedures that measure actual RRAM device behavior and use this information to adjust subsequent computations. This feedback loop compensates for device non-idealities and ensures that addition/subtraction operations achieve the required accuracy levels for neural network inference
3Use of energy by moving object
If RRAM devices are used for in-memory computing, then energy consumption is reduced, but non-ideal characteristics cause accuracy degradation
Solution Approach 1:
The patent replaces energy-intensive multiplication operations with low-energy addition/subtraction operations that naturally exploit RRAM's analog current summation capability. This substitution maintains the low energy consumption advantage of in-memory computing while reducing the impact of RRAM non-idealities on accuracy
Solution Approach 2:
The patent introduces calibration as an intermediary process that characterizes RRAM device behavior and compensates for non-ideal characteristics. This calibration enables accurate computation despite device variability, allowing the system to maintain both low energy consumption and high accuracy
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces hardware resource consumption, increases integration, and enhances the accuracy and robustness of AI accelerator chips by allowing addition/subtraction operations in RRAM-crossbar arrays, while mitigating the impact of RRAM non-idealities, resulting in high accuracy, low latency, and low energy consumption.
Implementation Method 1
A novel RRAM-crossbar hardware architecture is designed to perform addition/subtraction operations in parallel, using a ratio-based scheme that normalizes conductance values
Data Source
AI summary
A method of measuring cross-correlation or similarity between input features and filters of neural networks using an RRAM-crossbar architecture to carry out addition/subtraction-based neural networks for in-memory computing. The correlation calculations use L1 norm operations of AdderNet. The RCM structure of the RRAM-cross bar has storage and computing collocated, such that processing is done in the analog domain with low power, low latency and small area. In addition, the impact due to the nonidealities of RRAM device can be alleviated by the implicit ratio-based feature of the structure.