RRAM Data Storage Structure Mitigating Heat Accumulation

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Solution Overview

Problem

Resistive random access memory (RRAM) cells face limitations in switching cycles and data retention due to the accumulation of heat at the interface between dielectric layers, leading to the formation of additional oxygen vacancies and degradation of the conductive path, resulting in reduced reliability and endurance.

Innovation Solution

Incorporating a data storage structure with three dielectric layers, where the first layer has a strong bond between metal and oxygen atoms, and the second and third layers have progressively larger bandgaps, constraining the conductive path and mitigating the effects of heat accumulation, thereby increasing switching cycles and data retention.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional RRAM cell structure with two dielectric layers is used, then the device is simple to manufacture, but heat accumulation at the interface causes oxygen vacancy formation and reduces reliability

Engineering Contradiction:
ImproveRRAM cell reliability and enduranceVSAvoiddata storage structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent divides the data storage structure into three separate dielectric layers (first dielectric layer, second dielectric layer, and third dielectric layer) instead of using a conventional two-layer structure. This segmentation creates additional interfaces that distribute heat accumulation and prevent the formation of excessive oxygen vacancies at any single interface, thereby improving RRAM cell reliability and endurance while maintaining manufacturability through standard deposition processes

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent employs a composite dielectric structure where each layer can be formed from different materials with varying bandgaps and thermal properties. The first dielectric layer, second dielectric layer, and third dielectric layer are selectively designed with specific material compositions to optimize heat dissipation and oxygen vacancy suppression at each interface, creating a composite structure that enhances overall device reliability without significantly increasing manufacturing complexity

Inventive Principle:
Principle #40Composite materials

2Duration of action of stationary object

If the dielectric layers are designed with larger bandgaps to constrain the conductive path, then data retention is improved, but the manufacturing precision requirements increase

Engineering Contradiction:
Improvedata retentionVSAvoidbandgap control precision
Core Design Contradiction:
Duration of action of stationary objectVSManufacturing precision

Solution Approach 1:

The patent applies local quality by assigning different bandgap characteristics to different dielectric layers based on their specific functional requirements. The first dielectric layer, second dielectric layer, and third dielectric layer each have selectively optimized bandgap values that are tailored to their local position in the stack and their specific role in constraining the conductive path. This localized optimization allows each layer to contribute maximally to data retention while using standard material deposition techniques, avoiding the need for ultra-precise bandgap control across the entire structure

Inventive Principle:
Principle #3Local quality

3Duration of action of moving object

If heat accumulation at the dielectric interface is reduced to prevent oxygen vacancy formation, then switching cycle endurance is improved, but the thermal management complexity increases

Engineering Contradiction:
Improveswitching cyclesVSAvoidthermal management complexity
Core Design Contradiction:
Duration of action of moving objectVSDevice complexity

Solution Approach 1:

The patent segments the heat generation and dissipation pathways by introducing multiple dielectric layers with different thermal conductivities. The first dielectric layer, second dielectric layer, and third dielectric layer are positioned to create a distributed thermal management architecture where heat is progressively dissipated at each interface rather than accumulating at a single location. This segmentation approach extends the number of switching cycles the device can endure without requiring complex external thermal management systems

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces intermediate dielectric layers that act as thermal mediators between the high-density plasma CVD chamber environment and the underlying substrate. These intermediate layers (first dielectric layer, second dielectric layer, third dielectric layer) are specifically designed to manage heat flow during and after deposition, preventing excessive heat accumulation that would lead to oxygen vacancy formation. This intermediary approach protects the RRAM cell structure during manufacturing while maintaining simple operational thermal management

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The proposed structure enhances the number of switching cycles and data retention in RRAM cells by maintaining the integrity of the conductive path and reducing oxygen vacancy formation, leading to improved reliability and endurance.

Implementation Method 1

the first layer has a strong bond between metal and oxygen atoms

Methodology Applied
Scientific EffectChemical Bonding: Chemical Bonding

Implementation Method 2

the second and third layers have progressively larger bandgaps, constraining the conductive path

Methodology Applied
Scientific EffectBandgap:

Data Source

PatentUS12102019B2Data storage structure for improving memory cell reliability
Publication Date: 2024.09.24 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12102019B2 patent drawing
  • US12102019B2 patent drawing
  • US12102019B2 patent drawing

AI summary

Various embodiments of the present disclosure are directed towards an integrated chip. A first conductive structure overlies a substrate. A second conductive structure overlies the first conductive structure. A data storage structure is disposed between the first and second conductive structures. The data storage structure includes a first dielectric layer, a second dielectric layer, and a third dielectric layer. Respective bandgaps of the first, second, and third dielectric layers are different from one another.