RRAM Memory Structure With Direct Bottom Electrode Contact
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Solution Overview
Problem
The integration of Resistive Random-Access Memory (RRAM) devices into integrated chips poses challenges due to their height, which can lead to step height issues and process window problems in overlying interconnect layers, affecting yield and reliability.
Innovation Solution
The RRAM device design eliminates the bottom electrode via, allowing the bottom electrode to contact the overlying interconnect via directly, thereby reducing the overall height of the RRAM device to between 600 angstroms and 800 angstroms, mitigating step height differences and process window issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the RRAM device includes a bottom electrode via to contact the bottom electrode, then the electrical connection is established, but the overall device height increases causing step height issues and process window problems
Solution Approach 1:
The patent removes the bottom electrode via from the RRAM device structure, extracting this intermediate component that was causing height issues. The bottom electrode is reconfigured to directly contact the interconnect via, eliminating the via structure that created step height differences and process window problems while maintaining necessary electrical connections.
Solution Approach 2:
The patent merges the function of the bottom electrode and bottom electrode via by having the bottom electrode directly contact the interconnect via. This consolidation reduces the number of discrete components and eliminates the height penalty associated with the separate via structure, thereby reducing overall device height while preserving electrical connectivity.
2Manufacturing precision
If the RRAM device height is reduced to mitigate step height issues, then process window improves, but manufacturing complexity increases due to direct contact requirement
Solution Approach 1:
The interconnect via is designed to serve multiple functions: it provides both the electrical connection path and the structural support that would traditionally require a separate bottom electrode via. This multi-functional design simplifies the overall structure by eliminating redundant components while maintaining manufacturing precision and improving the process window.
Solution Approach 2:
The patent applies local quality by modifying the contact interface specifically at the bottom electrode region. The bottom electrode is configured with enhanced contact characteristics directly at the interconnect via interface, allowing for reliable electrical connection without requiring the additional height of a separate via structure, thus improving process window locally without compromising overall device functionality.
Data Source
AI summary
The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a memory device arranged over an etch stop material on a substrate. The memory device includes a data storage structure disposed between a bottom electrode and a top electrode. A first interconnect via contacts an upper surface of the bottom electrode and a second interconnect via contacts an upper surface of the top electrode. An insulating structure is arranged over and along opposing outermost sidewalls of the top electrode. The bottom electrode laterally extends to different non-zero distances past opposing outermost sidewalls of the insulating structure.