RRAM Memory Structure With Dual Storage Layers for Crystallization Stability

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Solution Overview

Problem

RRAM memory cells become unstable and degrade easily when the thickness of the storage element layer is reduced to minimize gate induced drain leakage, leading to reliability issues.

Innovation Solution

Implementing two storage element layers with different crystallization temperatures, where the first layer has a higher crystallization temperature than the second layer, to stabilize the RRAM memory cell by preventing crystallization induced by conductive filaments.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-generated harmful factors

If the thickness of the storage element layer is reduced to minimize gate induced drain leakage, then gate induced drain leakage is minimized, but the RRAM memory cell becomes unstable and degrades easily

Engineering Contradiction:
Improvegate induced drain leakageVSAvoidstability of RRAM memory cell
Core Design Contradiction:
Object-generated harmful factorsVSReliability

Solution Approach 1:

The storage element layer is divided into two separate layers: a first storage element layer with higher crystallization temperature and a second storage element layer with lower crystallization temperature. This segmentation allows each layer to serve a specific function - the first layer provides thermal stability while the second layer enables proper RRAM operation, thus resolving the contradiction between reducing gate induced drain leakage and maintaining reliability

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent uses composite material structure by combining two different storage element layers with distinct crystallization temperatures. This composite approach allows the device to simultaneously achieve low gate induced drain leakage (through thin total thickness) and high reliability (through the temperature-stable first layer that prevents degradation)

Inventive Principle:
Principle #40Composite materials

2Length of moving object

If the thickness of the storage element layer is reduced, then device dimensions are minimized, but crystallization induced by conductive filaments causes degradation

Engineering Contradiction:
Improvethickness of storage element layerVSAvoidresistance to crystallization
Core Design Contradiction:
Length of moving objectVSStability of the object's composition

Solution Approach 1:

Different regions of the storage element structure are assigned different crystallization temperatures - the first storage element layer has higher crystallization temperature to resist crystallization from conductive filament heat, while the second layer has lower crystallization temperature to enable proper RRAM switching. This local differentiation of material properties resolves the contradiction between thin dimensions and crystallization resistance

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The stability and reliability of the RRAM memory cell are improved by using two storage element layers with varying crystallization temperatures, reducing the likelihood of degradation due to high temperatures generated by conductive filaments.

Implementation Method 1

a crystallization temperature of the first storage element layer is higher than a crystallization temperature of the second storage element layer

Methodology Applied
Scientific EffectCrystallization: Crystallisation

Data Source

PatentUS20250228146A1Semiconductor device, memory structure and method of forming the same
Publication Date: 2025.07.10 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250228146A1 patent drawing
  • US20250228146A1 patent drawing
  • US20250228146A1 patent drawing

AI summary

A memory structure includes a bottom via, a memory cell and a top via. The memory cell is disposed on the bottom via and includes a bottom electrode, a top electrode and a first storage element layer and a second storage element layer sandwiched between the bottom electrode and the top electrode. The first storage element layer is in contact with the bottom electrode, and a crystallization temperature of the first storage element layer is higher than a crystallization temperature of the second storage element layer. The top via is disposed on the memory cell and electrically connected to the top electrode.