RRAM Dielectric Layout With Dummy Boundary Cell to Prevent Voids
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional resistive random access memory (RRAM) devices face issues with void formation between memory cells due to the poor gap-filling ability of low-k dielectric materials, leading to operation errors and reduced yield and reliability.
Innovation Solution
A manufacturing method for RRAM that involves forming a first low-k dielectric layer in the peripheral region and a gap-filling dielectric layer in the array region with different materials, including a dummy memory cell at the boundary to prevent simultaneous polishing and allow independent selection of dielectric materials, thereby avoiding cracks and improving yield and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a low-k dielectric material is formed between adjacent memory cells in the array region, then the operating speed of the logic circuit is improved, but the gap-filling ability is poor causing voids to form between memory cells
Solution Approach 1:
The patent divides the substrate into array region and peripheral region, and further divides the dielectric layer into first dielectric layer (in array region) and second dielectric layer (in peripheral region). This segmentation allows each region to use appropriate dielectric materials for their specific requirements, resolving the contradiction between operating speed and gap-filling ability.
Solution Approach 2:
The patent applies different dielectric materials to different regions: a first dielectric material with good gap-filling ability in the array region, and a second dielectric material with low-k properties in the peripheral region. This local differentiation allows each region to optimize for its specific function, eliminating voids while maintaining high operating speed.
2Reliability
If different dielectric materials are used in array region and peripheral region, then the operating speed and reliability are improved, but the process complexity increases due to simultaneous polishing requirements
Solution Approach 1:
The patent introduces a dummy memory cell structure at the boundary region before the polishing process. This preliminary structure allows the polishing process to be performed sequentially rather than simultaneously on different dielectric layers, simplifying the manufacturing process while maintaining the benefits of using different dielectric materials.
Solution Approach 2:
The dummy memory cell acts as an intermediary structure that facilitates the polishing process. It provides a reference surface and allows the polishing head to transition smoothly between different dielectric layers, reducing process complexity while enabling the use of different dielectric materials for improved reliability.
3Productivity
If a dummy memory cell is formed at the boundary, then cracks are avoided and yield is improved, but the device area increases
Solution Approach 1:
The dummy memory cell is formed partially at the boundary region between array and peripheral regions. It is not a complete memory cell structure but sufficient to provide the necessary polishing reference surface. This partial implementation achieves the yield improvement goal while minimizing the area overhead.
Data Source
AI summary
A method for manufacturing a resistive random access memory structure is provided. The method includes providing a substrate, and the substrate includes an array region and a peripheral region. The method includes forming a first low-k dielectric layer in the peripheral region, and the first low-k dielectric layer has a dielectric constant of less than 3. The method includes forming a plurality of memory cells on the substrate and in the array region. The method includes forming a dummy memory cell at a boundary between the array region and the peripheral region. The method includes forming a gap-filling dielectric layer on the substrate. The method includes forming a plurality of first conductive plugs in the gap-filling dielectric layer, and each of the plurality of first conductive plugs is in contact with one of the plurality of memory cells.