RRAM Erase Verification via Unified Word Line Voltage
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Solution Overview
Problem
Current nonvolatile semiconductor memory devices, particularly resistive RAM (RRAM) technology, face challenges in efficiently verifying the erase operation of memory cells, leading to potential incomplete erasure and increased power consumption due to the complexity of monitoring bit line currents across multiple word lines.
Innovation Solution
An erase verifying method is introduced that applies a first voltage to all word lines and a second voltage, typically ground voltage, to bit lines connected to memory cell blocks, sensing bit line currents and comparing them to a reference current to determine if the memory cells are sufficiently erased, with the option for a second erase operation if necessary, thereby simplifying the verification process and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional erase verification methods are used to monitor bit line currents across multiple word lines, then erasure completeness can be verified, but power consumption increases and the verification process becomes complex
Solution Approach 1:
The patent extracts the verification process from traditional complex monitoring methods and simplifies it by applying a unified first voltage to all word lines simultaneously. This reduces the verification mechanism to a simpler form that maintains accuracy while consuming less power, effectively taking out the unnecessary complexity from the original system.
Solution Approach 2:
The patent changes the voltage application parameters by applying a first voltage to all word lines at the same time during verification, rather than monitoring individual bit line currents across multiple word lines separately. This parameter change simplifies the verification process and reduces power consumption while maintaining erasure verification accuracy.
2Reliability
If traditional erase verification methods monitor each bit line individually across multiple word lines, then complete erasure can be confirmed, but the verification time and process complexity increase
Solution Approach 1:
The patent merges the verification of multiple word lines into a single unified process by applying the first voltage to all word lines simultaneously and performing a single verification operation. This combines what would traditionally be multiple separate verification steps into one operation, reducing process complexity while maintaining erasure completeness verification.
Solution Approach 2:
The verification method achieves multi-functionality by using a single verification process that can verify erasure completeness across all word lines connected to the memory cell block simultaneously. This universal verification approach replaces the need for individual word line verification, simplifying the overall process while maintaining reliability.
3Productivity
If a first voltage is applied to all word lines simultaneously with a second voltage to bit lines, then verification speed increases, but power consumption may increase
Solution Approach 1:
The patent applies voltage only to the extent necessary for verification - applying the first voltage to all word lines simultaneously and the second voltage to bit lines only during the verification operation itself, rather than continuously monitoring. This partial action approach achieves fast verification while avoiding excessive power consumption that would result from continuous monitoring.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method allows for rapid and accurate verification of memory cell erase operations across multiple word lines, ensuring complete erasure while minimizing power usage and time required for the erase verifying process.
Implementation Method 1
Variable resistance material films of RRAMs may show a reversible resistance variation according to a polarity or magnitude of an applied pulse
Data Source
AI summary
An erase verifying method includes applying a first voltage to a plurality of word lines connected to a memory cell block, and applying a second voltage less than the first voltage to a plurality of bit lines connected to the memory cell block. The method includes sensing bit line currents flowing through the plurality of bit lines, and comparing the sensed bit line currents with a reference current. The method also includes determining that the memory cell block has been sufficiently erased by a first erase operation if each of the sensed bit line currents is less than the reference current.