Resistive Random Access Memory Erase Techniques

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Solution Overview

Problem

Resistive-switching memory devices face retention issues due to conductive filaments in memory cells reverting to a programmed state after erasure, leading to short-term or long-term memory failures.

Innovation Solution

Implementing a modified erase process that includes a weak programming cycle following the initial erase cycle, using a weak programming signal to stabilize the memory state, and verifying the resistance state of memory devices to identify and address marginal or faulty cells.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a standard erase process is applied to memory cells, then the memory cells are erased from programmed state, but conductive filaments revert spontaneously to programmed state causing retention failure

Engineering Contradiction:
Improvememory retentionVSAvoiderase state stability
Core Design Contradiction:
ReliabilityVSStability of the object's composition

Solution Approach 1:

A weak programming pulse is applied immediately after the erase pulse to preemptively stabilize conductive filaments that have been partially disrupted. This preliminary action prevents spontaneous reversion to programmed state by reinforcing the erase state before thermal or electrical fluctuations can cause filament regrowth

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The invention introduces a dual-pulse sequence with different parameter characteristics: a strong erase pulse followed by a weak program pulse. The weak program pulse has lower amplitude and shorter duration, specifically tuned to stabilize marginal filaments without causing full re-programming, thereby changing the parameter profile to achieve stable erase state

Inventive Principle:
Principle #35Parameter changes

2Reliability

If a strong programming signal is used to ensure complete programming, then programming reliability improves, but marginal cells may be incorrectly programmed causing data errors

Engineering Contradiction:
Improveprogramming reliabilityVSAvoidprogramming precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The weak programming pulse applies partial action - insufficient to fully program robust cells but sufficient to stabilize marginal cells in the erase state. This selective partial action avoids over-programming while ensuring adequate stabilization of borderline cases

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The programming process is segmented into two distinct phases: a strong initial program pulse for complete programming, followed by a weak stabilization pulse that selectively affects only marginal cells. This segmentation allows differential treatment of cells based on their programming status

Inventive Principle:
Principle #1Segmentation

3Reliability

If multiple erase cycles are performed to ensure complete erasure, then erase completeness improves, but process time increases and cell stress accumulates

Engineering Contradiction:
Improveerase completenessVSAvoiderase process time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The weak programming pulse is applied continuously immediately after the erase pulse without interruption, maintaining the electrical field作用 on conductive filaments to prevent spontaneous recovery. This continuous action ensures complete erasure in a single cycle rather than requiring multiple discrete erase cycles

Inventive Principle:
Principle #20Continuity of useful action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Enhances the endurance and longevity of memory devices by reducing 'on' currents and narrowing the current distribution, preventing spontaneous reversion to a programmed state, thereby improving memory retention.

Implementation Method 1

Resistive-switching memory represents a recent innovation within the field of integrated circuit technology

Methodology Applied
Scientific EffectResistive switching:

Implementation Method 2

A read circuit coupled to the memory cell, wherein the read circuit is configured to apply a read voltage to the memory cell to thereby determine a state of the memory device

Methodology Applied
Scientific EffectElectrical resistance measurement: Electrical Resistance

Data Source

PatentUS11790999B2Resistive random access memory erase techniques and apparatus
Publication Date: 2023.10.17 CROSSBAR INC
  • US11790999B2 patent drawing
  • US11790999B2 patent drawing
  • US11790999B2 patent drawing

AI summary

A method for erasing a memory cell includes applying a first erase to memory cells to erase the memory cells, wherein first memory cells are in a weakly erased state in response to the first erase, and wherein second memory cells are in a normally erased state in response to the first erase, thereafter applying a first weak program to the memory cells, wherein the second memory cells enter a programmed state and the third memory cells remain in the erased state in response to the first weak program, and thereafter applying a read to the memory cells to identify the second memory cells, and applying a second erase to the second memory cells to thereby erase the second memory cells.