RRAM Array Error Back-Annotation for NAND Flash Disturb Mitigation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current memory technologies, such as NAND flash memory, face limitations in correcting errors due to high bit-error rates and inability to write corrected data back to individual memory cells, leading to inefficient error correction and accumulation of errors until entire pages or blocks need to be scrubbed.
Innovation Solution
A memory device with an error-correcting code (ECC) component and an error back-annotator that detects bit errors, generates corrected data, and writes it back to the memory cells, utilizing two-terminal memory architectures that allow bit-level addressing and re-writing without erasing adjacent cells, thereby reducing ECC logic and overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional ECC correction is used in NAND flash memory, then bit errors can be detected, but corrected data cannot be written back to individual memory cells, requiring entire pages or blocks to be scrubbed
Solution Approach 1:
The patent segments the error correction process into two distinct phases: detection phase where ECC detects bit errors in read data, and correction phase where identified erroneous cells are individually rewritten. This segmentation allows targeted correction of only affected cells rather than scrubbing entire pages or blocks, reducing the overhead and complexity of ECC operations while maintaining reliability.
Solution Approach 2:
The invention applies local quality by enabling individual memory cell addressing and selective rewriting. Instead of applying uniform error correction to entire pages or blocks, the system identifies and corrects only the specific cells containing errors. This localized approach reduces the resource waste and operational overhead associated with traditional ECC scrubbing methods.
2Reliability
If entire pages or blocks are scrubbed to correct errors, then reliability is maintained, but resource waste increases and device life is reduced
Solution Approach 1:
The patent divides the memory correction operation into cell-level granularity, allowing the system to identify and rewrite only the specific cells containing errors rather than scrubbing entire pages or blocks. This segmentation dramatically reduces the amount of data that needs to be read and rewritten, minimizing resource waste while maintaining error-free storage.
Solution Approach 2:
The invention applies partial action by performing error correction only on the subset of memory cells that actually contain errors, rather than applying uniform correction to all cells in a page or block. This partial correction approach eliminates unnecessary write operations and resource consumption while ensuring all erroneous data is corrected.
3Ease of operation
If two-terminal memory architectures are used, then bit-level addressing and re-writing is enabled, but manufacturing precision requirements increase
Solution Approach 1:
The patent leverages the self-service capability of two-terminal memory architectures, where the memory cells themselves provide the necessary control mechanisms for individual addressing and rewriting. The memory structure inherently supports selective cell access and data rewriting without requiring additional complex control circuitry, thereby enabling bit-level operation while mitigating manufacturing precision requirements.
Data Source
AI summary
A two-terminal memory array can be configured to address a single memory cell. A two-terminal memory array can further be configured to mitigate disturb errors associated with other types of memory (e.g., non-two-terminal memory such as NAND flash memory). Mitigation of disturb errors can allow re-writes and/or overwrites of data stored by the cells without a prior erase operation. In this regard, errors in the data read from a memory array can be corrected by error-correction code (ECC) and associated corrected data can be written back to the memory cells that store the portions of data determined by the ECC to be erroneous data and/or incorrect or bad data.