RRAM Manufacturing Uniform Resistance via Flat Metal Layer
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Solution Overview
Problem
The manufacturing process of conventional resistive random access memory (RRAM) results in uneven distribution of resistance, leading to inefficiencies in storage units.
Innovation Solution
A method involving forming a resistance layer on a flat first metal layer, followed by a passivation layer, etching to create basic units, depositing an insulating dielectric layer, forming contacting holes, and filling with a metal wire, ensures uniform resistance distribution by avoiding uneven oxidization and surface differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the conventional manufacturing process (filling tungsten plug, grinding and oxidizing) is used, then the manufacturing process is compatible with conventional MOS process, but the resistance distribution on the wafer becomes uneven
Solution Approach 1:
The patent applies preliminary action by first forming a flat metal layer base before depositing the resistance layer. This preliminary flat surface preparation ensures that subsequent oxidation produces uniform resistance distribution, preventing the unevenness that occurs when oxidizing irregular tungsten plugs. The flat base layer is prepared in advance to create optimal conditions for the resistance layer formation.
Solution Approach 2:
The patent introduces an intermediary flat metal layer between the substrate and the resistance layer. This intermediary layer serves as a mediator that provides a flat surface for resistance layer deposition, thereby ensuring uniform oxidation and resistance distribution while maintaining compatibility with conventional MOS manufacturing processes.
2Productivity
If tungsten plug grinding and oxidizing is performed, then a resistance layer can be formed, but uneven oxidization occurs leading to wire width limitations
Solution Approach 1:
The patent applies preliminary action by first forming a flat metal layer base before depositing the resistance layer. This preliminary flat surface preparation ensures that subsequent oxidation produces uniform resistance distribution, preventing the unevenness that occurs when oxidizing irregular tungsten plugs. The flat base layer is prepared in advance to create optimal conditions for the resistance layer formation.
Solution Approach 2:
The patent changes the physical parameter of the metal layer surface from irregular (grinded tungsten plugs) to flat (planarized metal layer). This parameter change in surface topology ensures uniform oxidation kinetics across the entire resistance layer, eliminating the wire width limitations and oxidation non-uniformity that plague the conventional approach.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method achieves uniform resistance distribution, enhancing the manufacturing process by preventing uneven oxidization and wire width limitations, thus improving the performance and reliability of RRAM storage units.
Implementation Method 1
oxidizing the resistance substrate layer to obtain an oxide of the resistance substrate layer, a resistance layer is formed
Implementation Method 2
depositing a insulating dielectric layer, and flattening the insulating dielectric layer
Implementation Method 3
depositing a nitride layer on the resistance layer by performing a chemical vapor deposition process
Data Source
AI summary
A manufacturing method of a resistive random access storage unit, includes: forming a resistance layer on a first metal layer having a flat surface; forming a passivation layer on the resistance layer; performing an etching process to obtain a plurality of basic units, a basic unit comprising a first metal layer, a resistance layer, and a passivation layer, which are laminated sequentially; depositing a insulating dielectric layer, and flattening the insulating dielectric layer; etching the insulating dielectric layer and the passivation layer to form contacting holes corresponded to the basic units; filling metal wires in the contacting holes; forming a second metal layer. According to the above method, a uniformly distributed resistance can be formed on a whole wafer.


