RRAM Devices with Reduced Forming Voltage via Metal Oxide Segmentation
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Solution Overview
Problem
Current RRAM devices require high forming voltages, which hinder their implementation in consumer products and reduce memory density, as they need more powerful transistors to generate higher voltages, and existing non-volatile memory technologies face issues with scalability and compatibility with CMOS logic processes.
Innovation Solution
Incorporating a second metal oxide material layer, such as titanium oxide, in addition to a primary metal oxide layer, along with an oxygen exchange layer, to reduce the forming voltage in RRAM elements, allowing for the integration of RRAM arrays with logic processors and enhancing the performance of embedded non-volatile memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a conventional single metal oxide material layer is used in RRAM devices, then the device structure is simpler, but the forming voltage is too high for integration with CMOS logic processes
Solution Approach 1:
The resistance switching layer is segmented into multiple metal oxide material layers with different compositions and thicknesses. This segmentation allows each layer to contribute differently to the overall resistance switching behavior, enabling voltage division and reducing the forming voltage required at each interface, thus achieving compatibility with CMOS logic processes while maintaining functional performance
Solution Approach 2:
The patent employs composite material structures by combining multiple metal oxide materials (such as HfO2, TiO2, Ta2O5, SiO2, Al2O3) in a stacked configuration. These composite layers create multiple interfaces with different band alignments and oxygen vacancy concentrations, which facilitate electron transport at lower voltages and reduce the overall forming voltage requirement while maintaining non-volatile memory functionality
2Reliability
If high forming voltage is used in RRAM devices, then the resistance switching function is achieved, but memory density decreases due to requirement of more powerful transistors
Solution Approach 1:
The patent systematically varies multiple parameters including the composition, thickness, and stacking sequence of different metal oxide layers. By optimizing these parameters, the forming voltage is reduced to levels compatible with standard CMOS transistors, allowing for higher transistor density and improved memory density while preserving the essential resistance switching function through controlled oxygen vacancy formation and filament growth
3Reliability
If existing non-volatile memory technologies are used, then memory functionality is provided, but scalability and compatibility with CMOS logic processes are limited
Solution Approach 1:
The multi-layer metal oxide structure serves multiple functions simultaneously: it provides non-volatile memory storage through resistance switching, enables low-forming voltage operation for CMOS compatibility, allows for scalable integration through standard semiconductor fabrication processes, and offers tunable electrical characteristics by adjusting layer compositions. This multi-functionality makes the technology adaptable to various application scenarios and scalable to advanced technology nodes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution significantly lowers the forming voltage, enabling the integration of RRAM arrays with logic processors and improving the performance and scalability of embedded non-volatile memory, addressing the limitations of traditional memory technologies.
Implementation Method 1
an oxygen exchange layer, to reduce the forming voltage in RRAM elements
Implementation Method 2
resistive random access memory (RRAM) stacks with reduced forming voltage
Data Source
AI summary
Approaches for fabricating RRAM stacks with reduced forming voltage, and the resulting structures and devices, are described. In an example, a resistive random access memory (RRAM) device includes a conductive interconnect in an inter-layer dielectric (ILD) layer above a substrate. An RRAM element is on the conductive interconnect, the RRAM element including a first electrode layer on the uppermost surface of the conductive interconnect. A resistance switching layer is on the first electrode layer, the resistance switching layer including a first metal oxide material layer on the first electrode layer, and a second metal oxide material layer on the first metal oxide material layer, the second metal oxide material layer including a metal species not included in the first metal oxide material layer. An oxygen exchange layer is on the second metal oxide material layer of the resistance switching layer. A second electrode layer is on the oxygen exchange layer.