RRAM FPGA Switching Block for High-Density Low-Power Interconnects
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Solution Overview
Problem
Field Programmable Gate Arrays (FPGAs) face limitations in achieving high component density, low power consumption, and fast read access due to the use of traditional SRAM memory cells, which are volatile and susceptible to electromagnetic radiation, and RRAM cross-point cells have parasitic currents and insufficient resistance ratios for sensitive applications.
Innovation Solution
The integration of RRAM memory cells with a voltage divider comprising programmable resistive elements and a pass gate transistor in FPGAs, allowing for independent programming circuitry that activates or deactivates signal intersections, improving the resistance ratio and reducing power consumption and parasitic currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional SRAM memory cells are used in FPGAs, then the FPGAs can be configured to implement logic functions, but the component density is limited and power consumption is high
Solution Approach 1:
The patent changes the fundamental parameter of memory cell type from volatile SRAM to non-volatile RRAM, enabling much smaller cell dimensions (e.g., 4F² vs traditional larger cells) and thereby increasing component density while reducing power consumption since RRAM does not require continuous refresh power
Solution Approach 2:
The patent extracts the configuration storage function from traditional SRAM blocks and implements it using RRAM cross-point cells, separating the volatile logic operation memory from the non-volatile configuration memory, thereby enabling higher density configuration storage
2Area of stationary object
If RRAM cross-point cells are used to increase component density, then area is reduced and power consumption is lowered, but parasitic currents increase and resistance ratio becomes insufficient
Solution Approach 1:
The patent introduces selector transistors (TFETs or MOSFETs) as intermediary devices between the RRAM cross-point cells and the read/write circuits. These selectors act as mediators that block parasitic currents from flowing through non-selected memory cells during read operations, thereby eliminating the harmful parasitic current effect while preserving the high density benefits
Solution Approach 2:
The patent segments the memory cell structure into distinct functional components: the RRAM cross-point cell for storage, selector transistors for current control, and read/write circuits for data access. This segmentation allows each component to be optimized independently, with selectors specifically designed to block parasitic currents
3Quantity of substance
If RRAM cross-point cells are used for high density, then component density increases, but read access speed becomes slow due to parasitic currents
Solution Approach 1:
The selector transistors serve as intermediary devices that enable fast read access by quickly turning on to allow current flow through selected cells and turning off to block current through non-selected cells. This mediation eliminates the parasitic current bottleneck and restores fast read access speeds while maintaining high density
Solution Approach 2:
The patent employs dynamically controllable selector transistors that can rapidly switch between on and off states based on selection signals. This dynamic control allows the memory array to quickly transition between read modes for different cells, enabling fast read access speeds comparable to or faster than traditional memory while maintaining high density
4Reliability
If SRAM memory cells are used in FPGAs, then configuration can be stored, but the memory is volatile and susceptible to electromagnetic radiation
Solution Approach 1:
The patent changes the fundamental parameter of memory volatility from volatile (SRAM) to non-volatile (RRAM), providing immunity to electromagnetic radiation and power loss. The RRAM cells retain their configuration data without continuous power, eliminating susceptibility to radiation-induced bit flips and power failure data loss
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances FPGAs by achieving higher component density, lower power consumption, and faster programming times while providing immunity to soft errors and electromagnetic radiation, making them suitable for a wider range of applications.
Implementation Method 1
RRAM is a non-volatile memory technology that induces a filament (or many filaments) in a dielectric material. In a normal state, the dielectric has high resistance, and is non-conductive. However, application of a suitable voltage across the dielectric can induce a conduction path therein.
Implementation Method 2
A RRAM memory cell is formed at respective intersections of the signal input lines and signal output lines. The RRAM memory cell can include a voltage divider comprising multiple resistive elements arranged electrically in series across a common-collector voltage (V cc) and source- supply voltage (Vss) of the RRAM memory cell.
Data Source
Figure 1
Figure 2
Figure 3A~3B
AI summary
Providing for a field programmable gate array (FPGA) utilizing resistive random access memory (RRAM) technology is described herein. By way of example, the FPGA can comprise a switching block interconnect having parallel signal input lines crossed by perpendicular signal output lines. RRAM memory cells can be formed at respective intersections of the signal input lines and signal output lines. The RRAM memory cell can include a voltage divider comprising multiple programmable resistive elements arranged electrically in series across a VCC and VSS of the FPGA. A common node of the voltage divider drives a gate of a pass gate transistor configured to activate or deactivate the intersection. The disclosed RRAM memory can provide high transistor density, high logic utilization, fast programming speed, radiation immunity, fast power up and significant benefits for FPGA technology.