RRAM-Based FPGA Using Voltage Divider and Pass Transistor
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Solution Overview
Problem
Field programmable gate arrays (FPGAs) face limitations in miniaturization, power consumption, and sensitivity due to the use of traditional SRAM memory cells, which are volatile, large in size, and susceptible to radiation, while RRAM technology offers potential benefits like higher density and lower power consumption but struggles with parasitic currents and resistance ratios suitable for sensitive applications.
Innovation Solution
The integration of RRAM memory cells with a voltage divider comprising programmable resistive elements and a pass gate transistor in FPGAs, allowing for fast programming and erasing, low power consumption, and improved resistance ratios through a voltage divider arrangement that activates or deactivates the pass gate transistor based on resistive states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional SRAM memory cells are used in FPGAs, then the FPGAs can be configured to implement logic functions, but the memory cells are large in size, consume more power, and are susceptible to radiation
Solution Approach 1:
The patent changes the fundamental parameter of memory cell type from volatile SRAM to non-volatile RRAM, which inherently provides radiation immunity while reducing cell size. The RRAM cell structure with resistive switching material enables smaller footprint and lower power consumption while maintaining configuration capability
Solution Approach 2:
The patent introduces a pass transistor as an intermediary element between the RRAM memory cell and the interconnect lines. This pass transistor enables selective readout of the RRAM cell state while preventing parasitic current from affecting other cells, thus enabling reliable radiation-immune operation
2Use of energy by stationary object
If RRAM memory cells are used in FPGAs, then higher density and lower power consumption are achieved, but parasitic currents and insufficient resistance ratios occur
Solution Approach 1:
The pass transistor serves as a mediator that controls current flow from the RRAM memory cell. It enables the low-power advantage of RRAM by allowing selective readout only when needed, while blocking parasitic current leakage to adjacent cells during non-read periods, thus resolving the parasitic current issue
Solution Approach 2:
The patent extracts the parasitic current problem from the RRAM cell by introducing separate read control circuitry (pass transistor) that isolates the memory cell from the interconnect during non-operational states, eliminating the harmful parasitic current effect while preserving the low-power benefit
3Area of stationary object
If RRAM memory cells are used in FPGAs, then smaller size and lower power consumption are achieved, but the resistance ratio is insufficient for sensitive applications
Solution Approach 1:
The pass transistor acts as an intermediary that amplifies and cleans up the resistance state signal from the RRAM cell. By controlling the gate voltage of the pass transistor, the circuit can selectively pass or block signals based on the RRAM cell state, effectively enhancing the resistance ratio for sensitive applications while maintaining the small cell size
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances FPGA technology by achieving smaller size, lower power consumption, and improved resistance ratios, enabling faster power-up and immunity to radiation and electromagnetic interference, making RRAM-based FPGAs suitable for a broader range of applications.
Implementation Method 1
each resistive element is characterized by a plurality of resistive states including a low resistive state and a high resistive state, wherein each resistive element is characterized a polarity, wherein the polarity for each resistive element is characterized by a high resistance state in response to a first voltage applied from the first electrode to the second electrode exceeding an erase voltage and is characterized by a low resistance state in response to a second voltage applied from the second electrode to the first electrode exceeding a programming voltage
Implementation Method 2
a voltage divider comprising multiple resistive elements arranged electrically in series across a common-collector voltage (VCC) and source-supply voltage (VSS) of the RRAM memory cell
Data Source
AI summary
A method for an FPGA includes coupling a first electrode of a first resistive element to a first input voltage, coupling a second electrode of a second resistive element to a second input voltage, applying a first programming voltage to a shared node of a second electrode of the first resistive element, a first electrode of the second resistive element, and to a gate of a transistor element, and changing a resistance state of the first resistive element to a low resistance state while maintaining a resistance state of the second resistive element, when a voltage difference between the first programming voltage at the second terminal and the first input voltage at the first terminal exceeds a programming voltage associated with the first resistive element.