RRAM Interconnect Landing Layout for Overlay-Tolerant Upper Electrode Contact
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Solution Overview
Problem
As feature sizes of RRAM devices decrease, it becomes increasingly difficult to accurately land an interconnect via onto the upper electrode, leading to poor electrical connections and potential device failure due to reduced process windows and larger critical dimension tolerances.
Innovation Solution
The integration of an upper interconnect wire that contacts the RRAM device's upper electrode, extending past its sidewalls, provides a larger process window and ensures a good electrical connection by being set back from the outermost sidewalls, thereby reducing the risk of overlay and critical dimension errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If feature sizes of RRAM devices are decreased to increase integration density, then device miniaturization is achieved, but manufacturing precision deteriorates due to reduced process windows and larger critical dimension tolerances
Solution Approach 1:
The patent transitions from a point-contact via model to a planar wire-contact model, where the interconnect wire makes contact with the upper electrode over an extended lateral area rather than at a single point. This dimensional change from 0D point contact to 2D planar contact provides tolerance to overlay and critical dimension variations, resolving the manufacturing precision issue while maintaining miniaturization.
Solution Approach 2:
The interconnect wire is formed to extend beyond the boundaries of the upper electrode before the actual contact is made. This preliminary extension ensures that even with manufacturing variations, the wire will overlap with the electrode, guaranteeing electrical connection. The wire acts as a pre-positioned tolerance buffer.
2Area of moving object
If feature sizes are decreased, then device miniaturization is achieved, but reliability deteriorates due to poor electrical connections and increased sensitivity to processing errors
Solution Approach 1:
By extending the interconnect wire laterally beyond the upper electrode boundaries, the patent creates an overlapping contact region that is insensitive to small misalignments. This dimensional extension transforms a fragile point-contact reliability issue into a robust planar overlap configuration.
Solution Approach 2:
The interconnect wire is strategically extended only in the regions adjacent to the upper electrode, creating localized overlapping zones where electrical contact is critical. The rest of the wire maintains its standard dimensions, optimizing material usage while ensuring connection reliability at the critical interface.
3Reliability
If interconnect via is landed directly onto upper electrode, then electrical connection is achieved, but process window is reduced making accurate landing difficult
Solution Approach 1:
Instead of making the upper electrode extend beyond the via (conventional approach), the patent inverts the geometry by having the interconnect wire extend beyond the upper electrode. This inversion provides the same tolerance benefit while maintaining proper electrical field confinement within the electrode boundaries.
Solution Approach 2:
The extended portions of the interconnect wire act as intermediary zones that mediate between the misaligned via and upper electrode. These extended wire regions provide alternative conduction paths that compensate for alignment errors, ensuring electrical connection even when the primary via-electrode alignment is imperfect.
Data Source
AI summary
The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first interconnect within a first inter-level dielectric (ILD) layer over a substrate. A memory device is disposed over the first interconnect and is surrounded by a second ILD layer. A sidewall spacer is arranged along opposing sides of the memory device and an etch stop layer is arranged on the sidewall spacer. The sidewall spacer and the etch stop layer have upper surfaces that are vertically offset from one another by a non-zero distance. A second interconnect extends from a top of the second ILD layer to an upper surface of the memory device.