RRAM Logical Operation Array Integrating Computation and Storage
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Solution Overview
Problem
Resistive random access memory (RRAM) is limited in performing operations solely and requires outputting operation results to external memory for storage, which is inefficient.
Innovation Solution
A method and apparatus that utilize a logical operation array in RRAM, involving field effect transistors and resistive random access memories, to perform logical operations and store results internally by controlling voltage states and signal inputs, allowing direct output of operation results.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If RRAM is used to perform logical operations, then computation capability is improved, but the operation result still needs to be output to external memory for storage
Solution Approach 1:
The patent merges computation and storage functions within the same RRAM device by integrating a logical operation unit with a storage unit. The operation unit performs logical operations on input signals and directly stores the operation results in the storage unit, eliminating the need to output results to external memory. This combines previously separate computation and storage components into a unified structure.
Solution Approach 2:
The RRAM device is designed with multi-functionality, where the same device can both perform logical operations and store data. The storage unit can store not only initial data but also the results of logical operations, allowing the device to serve multiple purposes within a single component, thereby reducing the need for separate external memory.
2Reliability
If operation results are output to external memory for storage, then data storage is achieved, but transmission bottleneck occurs
Solution Approach 1:
By merging the storage function into the RRAM device itself, the patent eliminates the need for data transmission to external memory. The operation results are stored directly within the device, removing the transmission bottleneck associated with the Von Neumann architecture while maintaining reliable data storage capability.
3Adaptability or versatility
If computation and storage are separated, then functional specialization is achieved, but Von Neumann bottleneck occurs
Solution Approach 1:
The patent combines computation and storage functions within the same RRAM device, creating an integrated structure that maintains functional specialization through distinct operation and storage units while eliminating the separation-induced transmission bottleneck. This allows the system to achieve both specialization and efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables integrated computation and storage within the RRAM, overcoming the need for external memory storage and enhancing operational efficiency by implementing logical operations and storage functions within the same component.
Implementation Method 1
turning on a first field effect transistor switch of at least one logical operation unit in the logical operation array, turning off a second field effect transistor switch of the logical operation unit
Implementation Method 2
a resistive random access memory (RRAM) serves as a next-generation non-volatile memory with high potential, and can implement reversible conversion between high resistance and low resistance under the action of an electrical impulse
Implementation Method 3
each logical operation unit includes the first resistive random access memory, the second resistive random access memory, the third resistive random access memory, the first field effect transistor switch, the second field effect transistor switch, and a voltage converter
Data Source
AI summary
A logical operation array of a resistive random access memory includes at least one logical operation unit; each logical operation unit includes multiple resistive random access memories, multiple field effect transistor switches and a voltage converter. The logical operation array is set for performing logical operation and enable to storage output level signal in one resistive random access memory after the logical operation


