RRAM Memory Bit Parallel Cell Coupling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Resistive random access memory (RRAM) arrays face challenges due to variations in operational characteristics across the array, leading to difficulties in distinguishing between high resistance state (HRS) and low resistance state (LRS) configurations, particularly with a 'tail' of memory cells having high resistivity that overlap, causing misidentification during read operations.
Innovation Solution
Coupling multiple memory cells into each memory bit, either in parallel or through specific architectures, to ensure that even if some cells have high resistivity, the overall resistivity remains low by summing currents, thereby creating a wider sensing window for accurate differentiation between HRS and LRS configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple memory cells are coupled in parallel to form memory bits, then the sensing window is widened and read accuracy is improved, but the storage density is reduced
Solution Approach 1:
The memory array is segmented into multiple memory cells per memory bit, with each cell contributing to the overall resistance measurement. This segmentation allows the system to overcome individual cell variability by aggregating multiple cells, thereby widening the sensing window between HRS and LRS while managing the trade-off through structured organization.
2Ease of operation
If memory cells are read by measuring resistance, then data can be retrieved, but variation in operational characteristics causes misidentification of HRS and LRS states
Solution Approach 1:
Multiple memory cells are merged into a single memory bit unit, where their combined resistance is measured rather than individual cell resistance. This merging approach averages out variations in operational characteristics across cells, enabling more reliable distinction between HRS and LRS states during read operations.
3Quantity of substance
If a single memory cell is used per memory bit, then storage density is maximized, but the sensing window is narrow making accurate reading difficult
Solution Approach 1:
The system changes the measurement parameter from individual cell resistance to aggregate resistance of multiple cells per memory bit. This parameter change amplifies the difference between HRS and LRS states, creating a wider sensing window that improves read accuracy while accepting a reduction in storage density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability and accuracy of read operations by widening the sensing window by at least an order of magnitude, improving signal-to-noise ratio and reducing misidentification errors, while acknowledging the trade-off of reduced storage density.
Implementation Method 1
Coupling multiple memory cells into each memory bit, either in parallel or through specific architectures, to ensure that even if some cells have high resistivity, the overall resistivity remains low by summing currents
Data Source
Figure 1
Figure 2
Figure 3
AI summary
Some embodiments include methods of storing and retrieving data for an RRAM array. The array is subdivided into a plurality of memory bits, with each memory bit having at least two memory cells. A memory bit is programmed by simultaneously changing resistive states of all memory cells within the memory bit. The memory bit is read by determining summed current through all memory cells within the memory bit. Some embodiments include RRAM having a plurality of memory cells. Each of the memory cells is uniquely addressed through a bitline/wordline combination. Memory bits contain multiple memory cells coupled together, with the coupled memory cells within each memory bit being in the same resistive state as one another.