RRAM Memory Tiling with Independent Tile Configuration
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Solution Overview
Problem
High performance tiling of partially configured RRAM memories is challenging due to the need for efficient configuration of arbitrary customer memories into basic memories without increasing the size of the configuration matrix.
Innovation Solution
A method involving independent calculation of memory enable and configuration signals for each memory tile, use of memory wrappers, address controllers, and OR blocks to combine output signals from non-configured and configured memories, allowing for efficient tiling of customer memories into a group of basic memories using a single memory mapping matrix.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional tiling methods are used for partially configured memories, then the configuration process becomes complex and requires multiple memory mapping matrices, but the device complexity and configuration matrix size increase significantly
Solution Approach 1:
The patent segments the memory matrix into multiple tiles, where each tile can be independently configured. This segmentation allows partial configuration of memories within tiles while maintaining a unified configuration approach, reducing the overall complexity compared to traditional methods that would require separate mapping matrices for each configuration scenario.
Solution Approach 2:
The patent implements a universal configuration matrix that can handle both fully configured and partially configured memories through a unified tiling methodology. This multi-functional approach eliminates the need for multiple specialized mapping matrices, thereby reducing device complexity while maintaining ease of manufacture.
2Adaptability or versatility
If arbitrary customer memories are tiled into basic memories using traditional methods, then memory customization is achieved, but the configuration matrix size increases unduly
Solution Approach 1:
The patent applies local quality by allowing different configuration states within different regions (tiles) of the memory matrix. Each tile can be configured according to specific customer requirements while maintaining a compact overall configuration structure, thus achieving high adaptability without proportionally increasing the configuration matrix size.
Solution Approach 2:
The patent introduces a tile-level organization dimension that separates the configuration problem into manageable chunks. By organizing memories into tiles with independent configuration capabilities, the system achieves arbitrary memory customization while keeping the configuration matrix compact through hierarchical organization.
3Productivity
If high performance tiling is attempted for partially configured memories, then memory performance is improved, but the tiling process becomes problematic and complex
Solution Approach 1:
The patent performs preliminary configuration actions by pre-organizing the memory matrix into tiles with defined configuration characteristics. This preliminary structuring enables high-performance tiling of partially configured memories while simplifying the overall tiling process, as the tile boundaries and configuration states are established in advance rather than determined during the tiling process itself.
Data Source
AI summary
A method of configuring a random access memory matrix containing partially configured memories in the matrix. The method includes the steps of independently calculating a memory enable signal and a configuration signal for a partially configured memory in each memory tile of the memory matrix. Memory tiles not supported by a memory compiler are determined. A memory wrapper is provided for each tile not supported by the memory compiler. An address controller is inserted in the memory matrix for each tile in a group of tiles. Output signals from each memory location in a memory group having a common group index are combined into a single output signal. A first stripe of memory tiles containing non-configured memory having a first width is selected. A second strip of memory tiles containing configured memory having a second width is also selected.