Self-Forming Metal Oxide Layers for RRAM Stability

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Solution Overview

Problem

Conventional RRAM devices face performance issues due to resistance variation in the variable resistive material layer, leading to decreased reliability and increased power consumption, and require additional fabrication steps for self-limiting current and circuitry.

Innovation Solution

Incorporating a constant resistance portion with self-forming metal oxide layers between the electrodes and the variable resistive material layer, which provides a constant resistance and reduces resistance variation, thereby eliminating the need for extra circuitry and simplifying the fabrication process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional RRAM devices are used with variable resistive material layer, then memory storage function is achieved, but resistance variation occurs leading to decreased reliability and increased power consumption

Engineering Contradiction:
Improvedevice reliabilityVSAvoidresistance variation
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent divides the resistive memory structure into distinct segments: a variable resistive material layer for data storage and a constant resistance portion with self-forming metal oxide layers for stability. This segmentation isolates the variable resistance function from the stability function, allowing each to optimize its performance independently, thereby reducing overall resistance variation and improving reliability

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The self-forming metal oxide layers act as intermediary elements between the electrodes and the variable resistive material layer. These intermediary layers provide a stable, constant resistance interface that buffers against variations in the variable resistive material, thereby reducing the impact of resistance variation on device reliability

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of operation

If additional circuitry is added to limit on/off current in conventional RRAM, then current control is improved, but device complexity and fabrication steps increase

Engineering Contradiction:
Improvecurrent limiting capabilityVSAvoidfabrication complexity
Core Design Contradiction:
Ease of operationVSDevice complexity

Solution Approach 1:

The constant resistance portion with self-forming metal oxide layers provides intrinsic current limiting capability within the memory structure itself. The self-forming nature of the metal oxide layers creates natural current pathways that limit on/off current without requiring external control circuitry, thereby maintaining ease of operation while reducing device complexity and fabrication steps

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The patent merges the current limiting function with the memory storage structure by integrating the constant resistance portion directly into the memory cell. This combination eliminates the need for separate current limiting circuitry, reducing overall device complexity while maintaining the necessary current control for reliable operation

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution enhances the reliability and reduces power consumption of RRAM devices by stabilizing the resistance, allowing for self-limited current without additional circuitry and simplifying the fabrication process.

Implementation Method 1

a constant resistance portion (108) that includes layers self-formed from interaction of the second electrode and the variable resistive material layer

Methodology Applied
Scientific EffectElectrical Resistance: Electrical Resistance

Data Source

PatentUS9112144B2Method of fabricating a resistive non-volatile memory device
Publication Date: 2015.08.18 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US9112144B2 patent drawing
  • US9112144B2 patent drawing
  • US9112144B2 patent drawing

AI summary

A method of fabricating a memory cell includes forming a bottom electrode on a substrate, a variable resistive material layer on the bottom electrode, and a top electrode on the variable resistive material layer. A first metal oxide layer interposes the top electrode and the variable resistive material layer. In an embodiment, the first metal oxide layer is a self-formed layer provided by the oxidation of a portion of the top electrode. In an embodiment, a second metal oxide layer is provided interposing the first metal oxide layer and the variable resistive material layer. The second metal oxide may be a self-formed layer formed by the reduction of the variable resistive material layer.