RRAM Cell Structure With Multi-Channel Soft Error Tolerance
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Solution Overview
Problem
RRAM devices are susceptible to soft errors during operation, leading to reliability issues, and existing methods to correct these errors often require additional circuits or cause delays, hindering miniaturization and speed improvement.
Innovation Solution
The RRAM device incorporates multiple channel regions in each resistive memory cell, with a resistance switching layer blanketly covering the bottom electrodes and insulating patterns, and a channel layer conformally covering the resistance switching layer and insulating patterns, allowing other channel regions to remain functional if one fails, and eliminating the need for patterning processes that can damage the resistance switching layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple channel regions are implemented in each resistive memory cell, then reliability is improved, but device complexity increases
Solution Approach 1:
The channel layer is segmented into multiple channel regions by insulating patterns that divide it into separate segments. Each channel region can independently conduct current, so if one region fails due to soft errors, other regions remain functional. This segmentation approach directly improves reliability while maintaining a relatively simple overall structure.
Solution Approach 2:
Different regions of the channel layer are given different functional qualities through the insulating patterns. The channel regions covering sidewalls of insulating patterns have specific electrical properties that enable independent conduction paths. This local differentiation allows multiple functional channels within a single memory cell structure.
2Manufacturing precision
If patterning processes are used to form channel regions, then manufacturing precision is improved, but the resistance switching layer suffers damage
Solution Approach 1:
The resistance switching layer is formed blanketly covering the bottom electrodes before any patterning processes are applied. This preliminary formation ensures the resistance switching layer is already in place and protected, avoiding subsequent damage from etching steps that would occur if patterning were performed after formation.
Solution Approach 2:
Instead of patterning the resistance switching layer to form channel regions (which would cause damage), the invention inverts the approach: the channel regions are formed by patterning the channel layer and insulating patterns while leaving the resistance switching layer intact as a blanket layer. This reversal of the conventional sequence eliminates damage to the resistance switching layer.
3Reliability
If additional circuits are added to correct soft errors, then reliability is improved, but device complexity and operation speed are degraded
Solution Approach 1:
The RRAM device corrects soft errors through its own multi-channel structure rather than requiring external correction circuits. The redundant channel regions provide inherent fault tolerance, allowing the device to self-correct errors by switching to functional channels when others fail. This eliminates the need for additional correction circuits and maintains simple device architecture.
Data Source
AI summary
A manufacturing method is provided. The method includes steps below. Forming bottom electrodes. Blanketly forming a resistance switching layer on the bottom electrodes. Forming a first insulating material layer on the resistance switching layer. Patterning the first insulating material layer to form insulating patterns. Conformally forming a channel layer having a plurality of channel regions on the resistance switching layer and the insulating patterns, wherein the plurality of channel regions are located on the resistance switching layer and cover opposite sides of the insulating patterns. Forming a second electrode material layer on the channel layer. Patterning the second electrode material layer to form top electrodes, each of the top electrodes is located in corresponding to one of the insulating patterns and covers at least two of the plurality of channel regions.


