RRAM OTP Memory Array With Lock-Bit Protection
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Solution Overview
Problem
Existing OTP memory devices face challenges in programming due to shrinking dimensions of fuse components, making it difficult to effectively program and secure sensitive information in integrated circuits.
Innovation Solution
Implementing a resistive random access memory (RRAM) cell array with a portion allocated for OTP operation and another portion for MTP, using a lock-bit generation circuit and smart write function to ensure secure one-time programming and data encoding/decoding, leveraging RRAM's variable resistance states to emulate logic outputs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If fuse component dimensions are reduced to increase integration density, then device miniaturization is improved, but programming reliability deteriorates
Solution Approach 1:
The patent changes the programming mechanism from traditional fuse breaking to RRAM resistance state switching. By applying voltage pulses to transition between high resistance state (HRS) and low resistance state (LRS), the system achieves reliable programming without mechanical stress on miniaturized components. This parameter-based control resolves the contradiction by enabling precise control at nanoscale dimensions.
Solution Approach 2:
The invention replaces the mechanical fuse-breaking process with an electrical resistance switching mechanism in RRAM cells. Instead of physically breaking or melting fuse material, the system uses voltage-controlled resistance transitions in oxide-based memristive devices, eliminating mechanical limitations and enabling reliable programming at smaller dimensions.
2Reliability
If RRAM cell array is used for OTP operation, then programming security is improved, but device complexity increases
Solution Approach 1:
The patent implements a unified RRAM cell array that serves both OTP and MTP functions through software-controlled programming modes. The same physical hardware structure can perform one-time programming for security applications or multiple-time programming for general storage, eliminating the need for separate OTP fuse structures and reducing overall device complexity.
Solution Approach 2:
The invention merges OTP and MTP memory functions into a single RRAM cell array structure. By combining the security-critical OTP functionality with general-purpose MTP capabilities in one unified device, the patent reduces the total number of components and simplifies the overall memory system architecture while maintaining programming security.
3Productivity
If voltage pulse is applied to program RRAM bit, then programming speed is improved, but energy consumption increases
Solution Approach 1:
The patent employs periodic voltage pulsing with optimized duration and amplitude to program RRAM cells. By using short, repeated voltage pulses rather than continuous high voltage, the system achieves fast programming speeds while allowing thermal dissipation between pulses, thereby reducing overall energy consumption compared to sustained high-voltage application.
Solution Approach 2:
The invention dynamically adjusts voltage pulse parameters (amplitude, duration, waveform) based on the programming state and cell characteristics. This parameter optimization enables the system to achieve reliable programming with minimal energy expenditure, resolving the contradiction between speed and energy consumption by finding the optimal pulse regime for each operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Provides an area-effective OTP solution that securely stores private codes, ensuring reliable one-time programming and data security by minimizing high operation voltages, while maintaining data integrity and preventing reprogramming.
Implementation Method 1
each of the plurality of first memory bits comprising a first access transistor and a first resistor coupled in series, the first resistor having a first variable resistance that is configured to be programmed from a first resistance to a second resistance based on an applied voltage pulse
Implementation Method 2
comparing the resistance of the at least one RRAM bit with a reference resistance
Data Source
AI summary
A memory device includes a first memory array including a plurality of first memory bits. Each of the plurality of first memory bits is configured as a one-time-programmable (OTP) memory bit. A second memory array includes a plurality of second memory bits, each of the plurality of second memory bits being configured as a multi-time-programmable (MTP) memory bit. A lock bit circuit operatively coupled to the first memory array and not the second memory array. The lock bit circuit is configured to generate a lock bit indicative of whether at least one of the plurality of first memory bits has been programmed.