RRAM OTP Memory with Lock-Bit Control for Secure Code Storage
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Solution Overview
Problem
Existing OTP memory devices face challenges in programming fuse components due to shrinking dimensions, leading to difficulties in programming and ensuring reliable data storage and security, particularly in resistive random access memory (RRAM) cells.
Innovation Solution
Implementing an RRAM cell array with a portion allocated for OTP operation and another portion for MTP, using a lock-bit generator to ensure a single polar direction write operation, and utilizing a smart write function to program private codes at chip probing, final testing, or in-field, with a low-program approach to minimize programming requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If fuse component dimensions are shrunk to increase storage capacity, then storage density is improved, but programming reliability deteriorates
Solution Approach 1:
The patent changes the programming mechanism from traditional fuse breaking to RRAM resistance state switching. By applying voltage pulses to transition between high-resistance and low-resistance states, the system achieves reliable programming without physical destruction, maintaining reliability even as dimensions shrink
Solution Approach 2:
The patent replaces the mechanical/physical fuse breaking process with an electrical resistance switching mechanism in RRAM cells. This substitution allows for non-destructive, reversible, and more reliable programming operations at smaller scales
2Quantity of substance
If RRAM dimensions are reduced to increase density, then storage density is improved, but programming difficulty increases
Solution Approach 1:
The patent utilizes resistance parameter changes in RRAM cells as the programming mechanism. By switching between high-resistance and low-resistance states through voltage application, the system provides clear, detectable programming states that are easy to verify even at reduced dimensions
Solution Approach 2:
The lock-bit generator provides feedback to verify successful programming by detecting the resistance state change. This feedback mechanism ensures programming completion is reliably detected, simplifying the programming operation despite smaller cell sizes
3Reliability
If a portion of RRAM is allocated for OTP operation, then security is improved, but available storage area is reduced
Solution Approach 1:
The patent implements multi-functionality in the RRAM cells, which can operate in either OTP mode or MTP mode depending on configuration. The same physical hardware provides both secure one-time programming capabilities and flexible multi-time programming, eliminating the need for separate dedicated areas
Solution Approach 2:
The patent merges OTP and MTP functionalities within the same RRAM array structure. By using configuration bits and the lock-bit generator, the system combines the security benefits of OTP with the flexibility of MTP in a unified storage solution, maximizing area utilization
4Reliability
If lock-bit generator is implemented to prevent re-programming, then data integrity is improved, but device complexity increases
Solution Approach 1:
The lock-bit generator acts as an intermediary mechanism between the RRAM cells and the programming circuitry. It monitors programming attempts and controls whether programming operations can proceed, providing data integrity protection without requiring complex control logic throughout the entire system
Solution Approach 2:
The lock-bit generator automatically detects programming completion and prevents further programming attempts without requiring external intervention. The system self-manages the OTP protection mechanism, reducing the need for additional control circuitry
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides an area-effective OTP solution that securely stores private codes in RRAM cells, ensuring reliable data storage and security by preventing further programming after initial setup, thus enhancing data integrity and security.
Implementation Method 1
each of the plurality of first memory bits comprising a first access transistor and a first resistor coupled in series, the first resistor having a first variable resistance
Data Source
AI summary
A memory device includes a first memory array including a plurality of first memory bits. Each of the plurality of first memory bits is configured as a one-time-programmable (OTP) memory bit. A second memory array includes a plurality of second memory bits, each of the plurality of second memory bits being configured as a multi-time-programmable (MTP) memory bit. A lock bit circuit operatively coupled to the first memory array and not the second memory array. The lock bit circuit is configured to generate a lock bit indicative of whether at least one of the plurality of first memory bits has been programmed.