Self-Aligned Passivation for RRAM Connection Resistance
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Solution Overview
Problem
The integration of resistive random access memory (RRAM) with copper damascene processing in crossbar arrays faces challenges such as increased connection resistance and the risk of electrical shorting due to the larger dimensions of copper lines compared to RRAM pillars, which damages conventional sidewall spacers during etching.
Innovation Solution
A self-aligned passivation layer is formed on the sidewalls of the RRAM structure, specifically aligned with the upper metal connection line, to prevent electrical shorting and protect the bottom electrode from damage during deep etching, allowing for reduced connection resistance and enabling scaling of RRAM pillar size without electrical shorts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional sidewall spacers are used without additional protection, then device complexity is reduced, but electrical shorting occurs during deep etching
Solution Approach 1:
The passivation layer is self-aligned to the RRAM stack, automatically positioning itself to provide protection where needed. This self-alignment mechanism eliminates the need for complex additional alignment steps or structures, maintaining device simplicity while ensuring electrical isolation during deep etching processes
Solution Approach 2:
The conformal deposition of the passivation layer changes the geometric parameters of the structure by adding a uniform protective thickness around the RRAM stack. This parameter change provides the necessary electrical isolation without requiring fundamental structural redesign, thus maintaining simplicity while preventing shorting
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces connection resistance and the likelihood of electrical shorting, facilitates integration with copper damascene processing, and enables scaling of RRAM pillar size below the contact size, enhancing the reliability and scalability of RRAM structures in crossbar arrays.
Implementation Method 1
A layer of resistive switching material is disposed between the top and bottom electrodes of the RRAM structure. The resistive switching material exhibits a measurable change in resistance under influence of at least an electric field and/or heat.
Implementation Method 2
Dielectric spacers are formed on sidewalls of at least the bottom electrode of the RRAM structure. The RRAM structure further includes a passivation layer formed on an upper surface of the dielectric spacers and covering at least a portion of sidewalls of the top electrode.
Data Source
AI summary
A resistive random access memory (RRAM) structure includes top and bottom electrodes electrically coupled with first and second metal connection lines, respectively, the first and second metal connection lines providing electrical connection to the RRAM structure. A layer of resistive switching material is disposed between the top and bottom electrodes of the RRAM structure. The resistive switching material exhibits a measurable change in resistance under influence of at least an electric field and/or heat. Dielectric spacers are formed on sidewalls of at least the bottom electrode of the RRAM structure. The RRAM structure further includes a passivation layer formed on an upper surface of the dielectric spacers and covering at least a portion of sidewalls of the top electrode. The passivation layer is self-aligned with the first metal connection line.