RRAM Sidewall Protection Layers for Etching Integrity

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Solution Overview

Problem

The narrow width of spacers in RRAM cells leads to etching failures during the manufacturing process, compromising the electrical performance of resistive random access memory (RRAM) devices.

Innovation Solution

A RRAM structure and manufacturing method involving protection layers with sidewall and extension portions are implemented, where the sidewall portions are disposed on the RRAM cell sidewalls and the extension portions connect between cells, preventing etching through and maintaining electrical performance without covering the top surfaces of the RRAM cells.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the width of the spacer is reduced to increase cell density, then the manufacturing precision deteriorates because the etching process cannot maintain the spacer integrity

Engineering Contradiction:
Improvecell densityVSAvoidspacer width control
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent introduces a protection layer as an intermediary substance deposited on the spacer structure. This protection layer has different etching resistance compared to the spacer material, allowing the etching process to selectively remove surrounding materials while preserving the spacer. The protection layer acts as a mediator that enables precise etching control at narrow dimensions where direct etching would fail.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If the spacer width is reduced to improve device integration, then the reliability deteriorates due to etching through the spacer causing electrical performance failure

Engineering Contradiction:
Improvedevice integrationVSAvoidelectrical performance
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The protection layer is deposited beforehand on the spacer structure to provide cushioning protection during the etching process. This pre-applied protective layer prevents the etching process from penetrating through the narrow spacer, thereby preventing electrical performance failure before it can occur. The protection layer absorbs the mechanical and chemical stress of the etching process.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

3Manufacturing precision

If protection layers are added to prevent etching through spacers, then the device complexity increases due to additional manufacturing steps

Engineering Contradiction:
Improvespacer protectionVSAvoidmanufacturing process steps
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The protection layer serves multiple functions simultaneously: it protects the spacer during etching, defines the spacer width through its thickness, and can serve as a mask for subsequent processing steps. By making the protection layer multi-functional, the patent reduces the need for additional separate layers or processes, thereby limiting the increase in device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS10153432B2Resistive random access memory structure and manufacturing method thereof
Publication Date: 2018.12.11 UNITED MICROELECTRONICS CORP
  • US10153432B2 patent drawing
  • US10153432B2 patent drawing
  • US10153432B2 patent drawing

AI summary

A resistive random access memory (RRAM) structure including a substrate, RRAM cells and protection layers is provided. The RRAM cells are adjacent to each other and disposed on the substrate. The protection layers are disposed respectively on sidewalls of the RRAM cells without covering top surfaces of the RRAM cells. Each of the protection layers includes a sidewall portion and an extension portion. The sidewall portion is disposed on each of the sidewalls of each of the RRAM cells. The extension portion is connected to a lower portion of the sidewall portion. An upper portion of the extension portion is lower than an upper portion of the sidewall portion. The extension portion is connected between the sidewall portions in a region between the RRAM cells.