RRAM Structure via Pull-Back Etching for Short Circuit Prevention
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Solution Overview
Problem
Existing manufacturing processes for resistive random access memory (RRAM) devices face challenges in scaling down while maintaining adequate resistance and electrical functionality, particularly in ensuring the appropriate thickness of electrodes and dielectric structures to prevent damage from high voltage and minimize the risk of short circuits.
Innovation Solution
A semiconductor structure is formed using a pull-back etching process that selectively etches the top and bottom electrodes while preserving the dielectric structure, allowing the dielectric width to exceed the electrode widths, and a hard mask structure is used to protect the electrodes during subsequent processes, enabling the formation of RRAM with appropriate resistance and electrical functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device scaling-down continues to increase density, then productivity and integration are improved, but manufacturing precision and reliability deteriorate due to difficulty in maintaining adequate electrode and dielectric thicknesses
Solution Approach 1:
Instead of reducing dielectric thickness to achieve smaller device dimensions, the patent inverts the approach by using a pull-back etching process that selectively removes electrode material while preserving the dielectric layer. This allows the dielectric width to remain larger than the electrode width, effectively solving the thickness control problem while maintaining scaling benefits
Solution Approach 2:
The patent changes the etching parameters by using a pull-back etching process with specific chemistry and conditions that selectively etch electrode materials (such as tungsten or copper) at different rates than the dielectric material. This parameter change enables precise control over the relative dimensions of electrodes and dielectric structures
2Length of moving object
If electrode and dielectric thicknesses are reduced for scaling, then device size is improved, but reliability worsens due to increased risk of short circuits and damage from high voltage
Solution Approach 1:
The patent inverts the conventional scaling approach by maintaining larger dielectric dimensions relative to electrodes through pull-back etching. This creates a structural configuration where the dielectric acts as a robust protective element, reducing the risk of short circuits while enabling smaller overall device footprints
Solution Approach 2:
The pull-back etching process creates a protective configuration beforehand where the dielectric structure extends beyond the electrode edges, providing a cushioning effect that prevents direct exposure of thin electrodes and reduces the likelihood of high-voltage damage and short circuits
3Ease of manufacture
If conventional etching processes are used, then manufacturing simplicity is maintained, but manufacturing precision deteriorates due to inability to selectively preserve dielectric structure
Solution Approach 1:
The patent modifies the etching process parameters by implementing a pull-back etching sequence with controlled chemistry and timing. This allows selective removal of electrode material while preserving the dielectric structure, achieving precise dimensional control without significantly complicating the manufacturing flow
Solution Approach 2:
The pull-back etching process is performed as a preliminary action before subsequent processing steps. By establishing the correct electrode-dielectric dimensional relationship early in the process, the patent enables easier formation of inter-metal dielectric layers and reduces the need for complex corrective steps later
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the manufacturing process by reducing the risk of short circuits and improving the yield by allowing for easier inter-metal dielectric layer formation between RRAM structures, while maintaining the necessary resistance and electrical functionality of the electrodes.
Implementation Method 1
a pull-back etching process is performed to etch the top electrode and the bottom electrode but not the dielectric structure
Data Source
AI summary
A semiconductor structure and a method for forming the same are provided. The method for manufacturing a semiconductor structure includes forming a bottom electrode layer over a substrate and forming a dielectric layer over the bottom electrode layer. The method for manufacturing a semiconductor structure further includes forming a top electrode layer over the dielectric layer and patterning the bottom electrode layer, the dielectric layer, and the top electrode layer to form a dielectric structure between a bottom electrode and a top electrode. The method for manufacturing a semiconductor structure further includes etching the bottom electrode from a sidewall of the bottom electrode to partially expose a bottom surface of the dielectric structure.