RRAM Read Circuit with Programmable Delay and Voltage
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Solution Overview
Problem
Current systems for reading resistive random access memory (RRAM) cells face challenges in accurately distinguishing between high and low resistance states due to variations in parasitic capacitance, resistance values, and switching element characteristics, which affects the reliability and efficiency of read operations.
Innovation Solution
A system comprising a resistive random access memory cell connected to a word line and a bit line, with a pre-charge circuit, driver circuit, comparator, latch, and pulse generator, where the delay is programmable based on parasitic capacitance, resistance values, and switching element characteristics, and the comparator includes an inverter with a selected threshold voltage to reduce supply voltage and prevent voltage stress, allowing for accurate sensing of resistance states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If fixed delay and voltage values are used in the read operation circuitry, then the device complexity is reduced, but the measurement precision of resistance states deteriorates due to variations in parasitic capacitance, resistance values, and switching element characteristics
Solution Approach 1:
The patent implements dynamic adjustment of delay values and voltage levels in the read operation circuitry. The delay value is programmably adjusted based on detected parasitic capacitance, resistance values, and switching element characteristics. The voltage level supplied to the comparator is dynamically adjusted based on the same parameters. This dynamic adaptation allows the system to maintain high measurement precision across varying operating conditions without requiring overly complex fixed-compensation circuitry.
Solution Approach 2:
The patent changes key operational parameters (delay time and voltage level) based on detected device characteristics. The delay value is modified according to parasitic capacitance, resistance values, and switching element properties. The comparator voltage is adjusted based on the same parameters. This parameter adaptation enables the system to compensate for variations in RRAM cell characteristics, improving resistance state distinction accuracy while avoiding the need for complex hardware compensation mechanisms.
2Measurement precision
If higher voltage is supplied to the comparator to improve sensing capability, then the measurement precision improves, but the power consumption and voltage stress on memory cells increase
Solution Approach 1:
The patent dynamically adjusts the voltage level supplied to the comparator based on detected device characteristics. Instead of using a fixed high voltage that maximizes sensing capability but also maximizes power consumption, the system optimizes the voltage parameter according to actual parasitic capacitance, resistance values, and switching element properties. This allows achieving sufficient measurement precision with minimized power consumption and reduced voltage stress on memory cells.
Solution Approach 2:
The patent incorporates feedback mechanisms where the detected characteristics of parasitic capacitance, resistance values, and switching elements are used to adjust the comparator voltage and delay parameters. This feedback loop enables the system to optimize the balance between sensing capability and power consumption, ensuring that only the necessary voltage level is applied to achieve accurate resistance state distinction without unnecessary energy expenditure or voltage stress.
3Reliability
If the delay is adjusted to account for process variations, then the reliability of read operations improves, but the device complexity increases
Solution Approach 1:
The patent implements programmable adjustment of the delay value based on detected process variations, parasitic capacitance, resistance values, and switching element characteristics. This dynamic delay adjustment compensates for manufacturing variations and ensures reliable read operations across different process conditions. The system achieves improved reliability without requiring overly complex timing control circuitry by using software-programmable delay adjustment rather than complex hardware compensation mechanisms.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The system enhances the accuracy and reliability of reading RRAM cells by programmably adjusting delays and voltages to distinguish between high and low resistance states, reducing power consumption and minimizing stress on the memory cells.
Implementation Method 1
The resistance of the insulating material increases when current is passed through the insulating material in one direction and decreases when current is passed through the insulating material in an opposite direction
Implementation Method 2
a pre-charge circuit configured to pre-charge the bit line to a first voltage with the word line being unselected
Implementation Method 3
a comparator configured to compare a second voltage on the bit line to a third voltage supplied to the comparator and generate an output based on the comparison
Implementation Method 4
a latch configured to latch the output of the comparator and to generate a latched output
Implementation Method 5
a pulse generator configured to generate a pulse after a delay subsequent to the first time to clock the latch to latch the output of the comparator
Data Source
AI summary
A system including a resistive random access memory cell connected to a word line and a bit line and a pre-charge circuit configured to pre-charge the bit line to a first voltage with the word line being unselected. A driver circuit selects the word line at a first time subsequent to the bit line being charged to the first voltage. A comparator compares a second voltage on the bit line to a third voltage supplied to the comparator and generates an output based on the comparison. A latch latches the output of the comparator and generates a latched output. A pulse generator generates a pulse after a delay subsequent to the first time to clock the latch to latch the output of the comparator and generate the latched output. The latched output indicates a state of the resistive random access memory cell.