RRAM Resistive Layer Uniformity via CMP Planarization
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Solution Overview
Problem
In the formation of resistive random-access memory (RRAM) devices, existing technologies face challenges in achieving uniformity and preventing current leakage due to the sensitivity of thin resistive material layers to surface and thickness non-uniformity, which affects the accuracy and reliability of memory cells.
Innovation Solution
The method involves forming RRAM cells with a bottom electrode layer, a resistive material layer, a capping layer, a top electrode, and spacers, using specific deposition techniques such as atomic layer deposition and chemical vapor deposition to achieve precise thickness and uniformity, and employing a first and second memory stop layer with CMP resistance properties to ensure accurate etching and layer alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If thin resistive material layers are used to achieve smaller memory cell size, then device scaling is improved, but uniformity and current leakage control deteriorate
Solution Approach 1:
The patent applies preliminary action by forming a planarization layer (CMP layer) before depositing the resistive material layer. This pre-planarization step ensures that the substrate surface is uniformly flat before the thin resistive material is deposited, preventing thickness non-uniformity that would otherwise occur due to surface irregularities. The CMP layer is formed in advance to compensate for underlying topography variations, enabling uniform thin layer formation.
Solution Approach 2:
The patent introduces a CMP layer as an intermediary between the substrate and the thin resistive material layer. This intermediate layer serves as a buffer that absorbs surface non-uniformities and provides a perfectly planar foundation for the resistive material deposition. The CMP layer mediates between the rough substrate surface and the requirement for uniform thin film deposition, allowing precise control of resistive material thickness.
2Volume of moving object
If thin resistive material layers are used to achieve smaller memory cell size, then device scaling is improved, but current leakage control deteriorates
Solution Approach 1:
The patent applies preliminary action by forming a planarization layer (CMP layer) before depositing the resistive material layer. This pre-planarization step ensures that the substrate surface is uniformly flat before the thin resistive material is deposited, preventing thickness non-uniformity that would otherwise occur due to surface irregularities. The CMP layer is formed in advance to compensate for underlying topography variations, enabling uniform thin layer formation.
Solution Approach 2:
The patent introduces a CMP layer as an intermediary between the substrate and the thin resistive material layer. This intermediate layer serves as a buffer that absorbs surface non-uniformities and provides a perfectly planar foundation for the resistive material deposition. The CMP layer mediates between the rough substrate surface and the requirement for uniform thin film deposition, allowing precise control of resistive material thickness.
3Ease of manufacture
If conventional deposition techniques are used, then process simplicity is maintained, but layer uniformity and thickness precision deteriorate
Solution Approach 1:
The patent introduces a CMP layer as an intermediary between the substrate and the thin resistive material layer. This intermediate layer serves as a buffer that absorbs surface non-uniformities and provides a perfectly planar foundation for the resistive material deposition. The CMP layer mediates between the rough substrate surface and the requirement for uniform thin film deposition, allowing precise control of resistive material thickness.
Solution Approach 2:
The patent employs atomic layer deposition (ALD) which fundamentally changes the deposition parameter from conventional physical vapor deposition to a chemically-controlled sequential process. ALD deposits material in atomic layers with precise thickness control through cycle counting, enabling sub-nanometer precision. The process parameters (temperature, pressure, precursor flow rates) are precisely controlled to achieve uniform conformal deposition across the substrate surface.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the uniformity of the electric field and increases the accuracy of memory cells by maintaining the integrity of the resistive material layer, reducing current leakage and improving the reliability of RRAM devices.
Implementation Method 1
subsequently depositing the resistive material layer and the capping layer thereover using atomic layer deposition
Implementation Method 2
employing specific deposition techniques such as atomic layer deposition and chemical vapor deposition
Implementation Method 3
The variations of the embodiments are discussed. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements. 0010. In operation 110 of method 100, as shown in FIG. 2, a semiconductor substrate having transistors and one or more metal/dielectric layers 210 over the transistors is provided.
Data Source
AI summary
A memory device includes a first inter-layer dielectric layer, plural conductive features, plural memory structures, a filler, and a second inter-layer dielectric layer. The conductive features are embedded in the first inter-layer dielectric layer. The memory structures are respectively over the conductive features. The filler is in between the memory structures. The second inter-layer dielectric layer is over the filler and the memory structures, and the second inter-layer dielectric layer and the filler form an interface, in which the interface extends from one of the memory structures to another of the memory structures.