RRAM-Based Round Robin Arbitration for Scalable Requestor Arrays
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Solution Overview
Problem
Existing arbitration systems face challenges in handling a large number of requestors due to timing requirements and area constraints, particularly when using combinatorial logic and registers, which are limited in number and size.
Innovation Solution
A round robin arbitration method utilizing a requestor random access memory (RRAM) with entries for each requestor, including a valid field to indicate request status, allowing for efficient arbitration of up to 1,024 or more requestors by scanning the RAM and selecting winners based on valid and credit fields, optionally using multiple RAMs and multi-level arbitration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If combinatorial logic and registers are used for arbitration, then arbitration can be performed for a small number of requestors, but the system cannot meet timing requirements and requires significant area when the number of requestors increases
Solution Approach 1:
The patent replaces combinatorial logic circuits with a memory-based system. Instead of using complex combinatorial logic to arbitrate between N requestors, the system uses a memory structure with N entries, where each entry corresponds to a requestor. The arbitration is performed by writing to and reading from memory locations, which is more area-efficient and scalable than traditional combinatorial logic approaches.
Solution Approach 2:
The patent changes the fundamental parameter of arbitration from logic-based selection to memory-address-based selection. By using memory addresses to represent requestors and controlling memory access patterns, the system can handle a large number of requestors without proportionally increasing area. The key parameter change is from using logic gates and registers to using memory cells and address decoders.
2Adaptability or versatility
If combinatorial logic and registers are used for arbitration, then arbitration can be performed for a small number of requestors, but timing requirements cannot be met when the number of requestors increases
Solution Approach 1:
The patent substitutes combinatorial logic with memory-based arbitration, which provides more predictable and controllable timing characteristics. Memory access times are regular and can be synchronized with system clock cycles, allowing the arbitration process to meet timing requirements even when the number of requestors increases to 1,024 or more.
3Ease of operation
If registers and combinatorial logic are used, then arbitration is simple for a small number of requestors, but the system requires significant area to fabricate
Solution Approach 1:
The patent replaces area-intensive combinatorial logic circuits with a compact memory structure. The memory-based arbitration system uses N memory entries instead of complex logic networks, significantly reducing the fabrication area while maintaining arbitration functionality for a large number of requestors.
Solution Approach 2:
The memory structure serves multiple functions: it stores requestor identifiers, tracks arbitration states, and enables selection of winning requestors. This multi-functionality eliminates the need for separate logic circuits for each function, reducing overall area while maintaining operational simplicity.
Data Source
AI summary
A circuit performs a method of arbitrating requests between multiple requestors. The method includes accessing, via an arbitration processor, a requestor random access memory (RRAM) having multiple entries. Each entry corresponds to a requestor and includes a valid field indicating whether or not the requestor is requesting. One of the multiple entries is selected in a round robin manner as a function of a value in the valid field indicative of the corresponding requestor requesting. The corresponding requestor requesting arbitration is notified.