RRAM Self-Sputtering Spacer for Narrow Bit Pitch
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Solution Overview
Problem
As RRAM cells scale down, the narrow bit-to-bit pitch makes it difficult to form sidewall spacers, leading to potential damage and performance degradation due to increased processing challenges and larger cell sizes from thick spacers.
Innovation Solution
A self-sputtering spacer is formed using a sputter etching process, creating a narrow vertical and lateral structure that minimizes cell size and eliminates processing issues by redepositing spacer material onto the RRAM cell components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional conformal dielectric layers and etching processes are used to form sidewall spacers, then the spacers provide structural support and protection, but the spacers become thick and increase the lateral dimension of the RRAM cell
Solution Approach 1:
The patent changes the formation method of the sidewall spacer from conventional conformal dielectric deposition and etching to atomic layer deposition (ALD). This parameter change in the deposition process enables precise control of spacer thickness, achieving thin spacers (e.g., 5-10 nm) that reduce the lateral dimension of the RRAM cell while maintaining adequate structural support and protection during subsequent processing steps.
2Area of stationary object
If RRAM cells are scaled down to reduce cell size, then higher density is achieved, but the narrow bit-to-bit pitch makes it difficult to form sidewall spacers and increases processing challenges
Solution Approach 1:
The patent replaces the conventional mechanical/chemical etching process with atomic layer deposition (ALD) to form the sidewall spacer. This substitution of the formation mechanism enables precise thickness control and conformal coverage even at narrow bit-to-bit pitches, making spacer formation feasible and reliable at scaled dimensions where conventional etching processes fail.
Solution Approach 2:
By changing the deposition method to ALD and controlling deposition parameters such as precursor flow, temperature, and cycle number, the patent achieves uniform thin spacer formation at scaled dimensions. This parameter control enables spacer formation in narrow pitches while maintaining manufacturing ease and process reliability.
3Reliability
If thick sidewall spacers are formed to ensure structural integrity, then protection is provided, but the cell size increases and performance degrades
Solution Approach 1:
The patent uses ALD to precisely control spacer thickness at the nanometer scale, forming thin spacers (5-10 nm) that provide sufficient structural integrity and protection during processing. This precise parameter control eliminates the need for thick spacers, thereby reducing cell size and improving performance and density while maintaining adequate protection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the lateral dimension of RRAM cells, enhances their performance, and prevents damage by forming a thinner, more effective spacer without the need for conformal dielectric layers and etching processes.
Implementation Method 1
The self-sputtering spacer is formed by performing a sputter etching process on a spacer material vertically arranged between the resistance switching layer and a bottom etch stop layer
Data Source
AI summary
The present disclosure relates to an integrated circuit device having an RRAM cell, and an associated method of formation. In some embodiments, the integrated circuit device has a bottom electrode disposed over a lower metal interconnect layer. The integrated circuit device also has a resistance switching layer with a variable resistance located on the bottom electrode, and a top electrode located over the resistance switching layer. The integrated circuit device also has a self-sputtering spacer having a lateral portion that surrounds the bottom electrode at a position that is vertically disposed between the resistance switching layer and a bottom etch stop layer and a vertical portion abutting sidewalls of the resistance switching layer and the top electrode. The integrated circuit device also has a top etch stop layer located over the bottom etch stop layer abutting sidewalls of the self-sputtering spacer and overlying the top electrode.