RRAM Word-Line Architecture with Shared Selection Transistor
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Solution Overview
Problem
Current RRAM memory array architectures face challenges in achieving high-density, fast response times, low power consumption, and reduced complexity in programming and decoding circuitry, with existing designs either suffering from area overhead, sneak path currents, or complex switching circuitry.
Innovation Solution
A memory circuit architecture that groups memory cells into words, sharing a single selection transistor and using a simplified control method with reduced access points, applying positive and negative voltages to set and reset states directly, and eliminating the need for source line drivers, thereby reducing complexity and increasing density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional 1T1R memory cell architecture is used, then each memory cell has dedicated selection transistor and source line, but this causes area overhead and increased device complexity
Solution Approach 1:
Multiple memory cells in a word are shared with a single selection transistor, merging the selection function across multiple cells. This reduces the total number of transistors and control circuits required, directly addressing the complexity issue while maintaining reliable control through the shared transistor's ability to selectively enable/disable the entire word.
Solution Approach 2:
The selection transistor serves multiple memory cells simultaneously, making it a universal control element. This multi-functionality reduces the per-cell overhead of dedicated selection transistors and source lines, thereby reducing overall device complexity while maintaining control reliability through the transistor's switching capability.
2Area of moving object
If a crossbar architecture without selection transistors is used, then area density is maximized, but sneak path currents occur and reading accuracy deteriorates
Solution Approach 1:
The memory array is segmented into words, with each word sharing a common selection transistor. This segmentation allows selective activation of specific words while keeping others inactive, preventing sneak path currents from unselected words and ensuring reading accuracy, while maintaining high area density through the shared transistor approach.
3Ease of operation
If three access points (bit line, source line, word line) are used for each memory cell, then complete control is achieved, but this increases the number of control circuits and decoding complexity
Solution Approach 1:
Multiple memory cells share a common selection transistor and ground connection, merging their control functions. This reduces the number of separate control circuits needed, as the shared transistor and ground line serve all cells in the word simultaneously, thereby reducing decoding complexity while maintaining complete control capability through the shared access points.
4Device complexity
If selection transistors are shared across multiple memory cells, then device complexity is reduced, but leakage current between cells increases
Solution Approach 1:
The memory array is segmented into words with each word sharing a common selection transistor. When a word is not selected, the shared transistor blocks current flow to all cells in that word, preventing leakage current from affecting other words. This segmentation approach reduces complexity while managing leakage through word-level isolation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a high-density memory array with low leakage current and reduced complexity, minimizing the need for complex addressing and control routing circuitry, while maintaining energy efficiency and access time performance.
Implementation Method 1
The resistive layer RL forms a resistive switch between a high resistance state (HRS) and a low resistance state (LRS) that are arbitrarily assigned to logical levels 0 and 1, respectively or conversely
Data Source
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AI summary
The invention relates to a method for controlling a memory cell (VR), the method comprising: during set and reset phases, selecting the memory cell by setting a selection transistor (ST) in a conducting state, linking a first electrode (BE) of a variable resistor (VR) of the memory cell to a ground voltage; during the set phase, setting a second electrode (TE) of the variable resistor to a high positive voltage (STV); and during the reset phase, setting the second electrode of the variable resistor to a high negative voltage (RSV).