RRAM Source Line Cross-Section Scaling for Reset Speed
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Solution Overview
Problem
The durability of RRAM devices with 1T1R architecture is limited by the lifetime of transistors, which age primarily during the reset operation, requiring higher voltages and resulting in reduced performance and durability due to high RC delay in metal interconnect layers.
Innovation Solution
Increasing the cross-sectional area of source lines from conventional wire sizes in lower metal interconnect layers to larger sizes in higher layers, such as from M2 to M6, reduces sheet resistance and enhances reset speed, thereby increasing transistor lifetime and RRAM device durability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional wire sizes in lower metal interconnect layers (M2) are used for source lines, then device complexity is reduced, but RC delay increases resulting in slower reset speed and reduced transistor lifetime
Solution Approach 1:
The patent transitions the source line from a two-dimensional planar connection in lower metal layers to a three-dimensional vertical connection spanning multiple metal layers (M2 through M6). This dimensional change allows the source line to achieve larger cross-sectional area and lower sheet resistance by utilizing the vertical stacking of metal layers, thereby reducing RC delay and improving reset speed without compromising device functionality
Solution Approach 2:
The source line is implemented as a nested structure where multiple metal layer segments are vertically stacked and electrically connected through vias. This nesting approach allows the source line to effectively occupy and utilize the vertical space between M2 and M6 layers, creating a low-resistance path that behaves electrically like a single thick conductor while maintaining compatibility with the standard multi-layer interconnect architecture
2Reliability
If higher voltages are applied during reset operation to improve switching, then memory cell switching performance is improved, but transistor aging accelerates reducing device durability
Solution Approach 1:
The patent changes the electrical parameter of the source line by increasing its cross-sectional area through vertical stacking of metal layers. This parameter change reduces the sheet resistance and RC delay of the source line, enabling more efficient current delivery during reset operations. The improved electrical characteristics allow for reduced voltage stress on the transistor while maintaining effective reset functionality, thereby extending transistor lifetime and improving device durability
3Reliability
If larger cross-sectional area source lines are used in higher metal layers, then sheet resistance decreases improving reset speed, but manufacturing precision requirements increase
Solution Approach 1:
The patent utilizes the existing multi-layer metal interconnect structure, which is already part of the standard CMOS fabrication process, to create the low-resistance source line. By making the source line multi-functional (serving both as a standard interconnect and as a low-resistance current path), the invention avoids requiring separate manufacturing processes or additional precision steps. The approach leverages the universal multi-layer metal structure already present in modern semiconductor devices
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces reset operation time by approximately one order of magnitude and extends the lifetime of RRAM transistors and devices by a similar margin, improving overall performance and reliability.
Implementation Method 1
Increasing the cross-sectional area of source lines from conventional wire sizes in lower metal interconnect layers to larger sizes in higher layers, such as from M2 to M6, reduces sheet resistance and enhances reset speed
Data Source
AI summary
Some embodiments relate to an integrated circuit device including an array of memory cells disposed over a semiconductor substrate. An array of first metal lines are disposed at a first height over the substrate and are connected to the memory cells of the array. Each of the first metal lines has a first cross-sectional area. An array of second metal lines are disposed at a second height over the substrate and are connected to the memory cells of the array. Each of the second metal lines has a second cross-sectional area which is greater than the first cross-sectional area.