1T1R RRAM Cell Spacer Prevents Sidewall Leakage

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Solution Overview

Problem

Current one transistor and one resistive random access memory (1T1R) cell architectures suffer from significant leakage current issues due to sidewall damage and polymer residues during the formation of conduction paths in resistive random access memory (RRAM) devices, leading to inefficient device performance.

Innovation Solution

Incorporating a spacer around the capping layer and top electrode to prevent sidewall damage and polymer residue-induced leakage paths, while using a specific layer structure and material combinations for electrodes and resistive materials to enhance the RRAM cell's operational reliability and efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If a 1T1R cell architecture is used to improve random access time, then switching speed is improved, but leakage current increases significantly

Engineering Contradiction:

Improverandom access timeVSAvoidleakage current

Core Design Contradiction:

SpeedVSLoss of energy

Solution Approach 1:

A spacer layer is introduced as an intermediary protective element between the etching process and the resistive material layer sidewalls. This spacer acts as a mediator that prevents direct contact between the etchant and the resistive material, thereby preventing polymer residue formation and sidewall damage that lead to leakage paths, while allowing the 1T1R architecture to maintain its fast switching performance.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The spacer is formed preliminarily before the bottom electrode etching process. By preparing this protective layer in advance, the resistive material layer sidewalls are pre-protected against etching damage and polymer residue formation, preventing leakage path formation before they can occur during the etching operation.

Inventive Principle:

Principle #10Preliminary action

2Ease of manufacture

If etching is performed to form bottom electrode patterns, then device fabrication is enabled, but sidewall damage and polymer residues create leakage paths

Engineering Contradiction:

Improvebottom electrode patterningVSAvoidleakage current

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

The spacer serves as a protective intermediary layer that is deposited conformally on the resistive material layer before etching. This intermediary layer allows the etching process to proceed for bottom electrode patterning while preventing the etchant from directly damaging the resistive material sidewalls or forming polymer residues that would create leakage paths.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The spacer provides beforehand cushioning protection to the resistive material layer sidewalls. By placing this protective layer in advance, it absorbs and prevents the harmful effects of the etching process, cushioning the resistive material against sidewall damage and polymer residue formation that would otherwise create leakage paths during bottom electrode patterning.

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The spacer effectively reduces leakage currents and maintains the integrity of the resistive material layer, improving the RRAM cell's switching performance and reducing the formation of unintended conducting paths, thereby enhancing the overall efficiency and reliability of the memory device.

Implementation Method 1

Incorporating a spacer around the capping layer and top electrode to prevent sidewall damage and polymer residue-induced leakage paths

Methodology Applied

Scientific EffectPhysical barrier protection:

Implementation Method 2

RRAM devices operate under the principle that a dielectric, which is normally insulating, can be made to conduct through a filament or conduction path formed after the application of a sufficiently high voltage

Methodology Applied

Scientific EffectFilament formation through high voltage stress:

Data Source

PatentUS10038139B2One transistor and one resistive random access memory (RRAM) structure with spacer

Publication Date: 2018.07.31 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

The present disclosure provides a resistive random access memory (RRAM) cells and methods of making the same. The RRAM cell includes a transistor and an RRAM structure. The RRAM structure includes a bottom electrode having a via portion and a top portion, a resistive material layer on the bottom electrode having a width that is same as a width of the top portion of the bottom electrode; a capping layer over the bottom electrode; a spacer surrounding the capping layer; and, a top electrode on the capping layer having a smaller width than the resistive material layer. The RRAM cell further includes a conductive material connecting the top electrode of the RRAM structure to a metal layer.