RRAM Spacer Stack Shields Switching Region From Etch Damage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Non-volatile memory devices, such as RRAM, are vulnerable to etch damage during fabrication, leading to non-uniformity in the switching region and increased variability in resistive switching characteristics due to traditional lithography processes.
Innovation Solution
A semiconductor device structure is developed with a substrate, base dielectric layer, first electrode, mask structure, and spacer stack that includes a resistive switching element lining the sidewalls of the mask and electrode, protecting the switching region from etch processes and providing a confined switching area for improved uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional lithography processes are used to etch the top electrode and bottom electrode layers, then the fabrication process is simple and straightforward, but etch damage regions are created near the switching region leading to non-uniformity and increased variability in resistive switching characteristics
Solution Approach 1:
The patent applies preliminary action by forming the resistive switching element and confining the switching region before performing the electrode etching processes. The switching region is prepared and protected in advance, so that when etching occurs, the damage does not affect the critical switching area. This resolves the contradiction by ensuring manufacturing precision is established before the harmful etch process occurs.
Solution Approach 2:
The patent introduces an intermediary structure (the confining structure or mask) that mediates between the etching process and the switching region. This intermediary protects the switching region from direct exposure to etch damage while still allowing the electrodes to be formed. The intermediary structure acts as a buffer that prevents the harmful effects of etching from reaching the critical switching area.
2Ease of manufacture
If traditional etch processes are used during fabrication, then the manufacturing process is straightforward, but etch damage regions limit the performance of the memory devices
Solution Approach 1:
The patent converts the harmful etch process into a beneficial one by carefully controlling the etching to create well-defined electrode structures while the confining structure protects the switching region. The etch process, when properly managed with the confining structure in place, creates precise electrode geometries without damaging the switching region, thus transforming a harmful process into one that benefits device performance.
Solution Approach 2:
The confining structure serves as an intermediary that allows the etch process to proceed without damaging the switching region. It mediates between the necessary electrode formation etching and the protection of the switching region, enabling the etch process to be performed while maintaining device reliability.
3Ease of manufacture
If the switching region is exposed to etch processes, then electrode formation is achieved, but non-uniformity in the layers near the switching region increases variability in resistive switching characteristics
Solution Approach 1:
The confining structure is formed before the electrode etching process, preliminarily establishing the boundaries of the switching region. This preliminary action ensures that when etching occurs, the uniformity near the switching region is preserved because the confining structure prevents etch damage from affecting this critical area.
Solution Approach 2:
The confining structure acts as an intermediary barrier during the electrode formation etch process. It allows the electrodes to be formed through controlled etching while simultaneously protecting the switching region from non-uniformity and damage, thus maintaining manufacturing precision during electrode formation.
Data Source
AI summary
In a non-limiting embodiment, a device may be formed having a substrate that has at least a first region. A base dielectric layer is arranged over the substrate. The base dielectric layer includes an interconnect in the first region. A first electrode is arranged over the interconnect in the first region. A mask structure is arranged over the first electrode. At least one spacer stack is arranged at least partially around the mask structure and the first electrode. The spacer stack(s) includes a resistive switching element at least partially lining sidewalls of the mask structure and the first electrode, and a second electrode arranged over the resistive switching element.