RRAM Sidewall Spacer Resistance Layer for Filament Stability
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Solution Overview
Problem
As semiconductor memory devices shrink, the variation in the quantity of conduction filaments in resistive random access memory (RRAM) devices becomes critical, affecting device reliability, and there is a need for an improved RRAM structure and fabrication method to maintain stability and scalability.
Innovation Solution
The RRAM device features a dual spacer-type resistance layer and top electrode configuration on opposite sidewalls of a word line, with diodes coupled to the electrodes, allowing for a minimum cell size of 2F^2 and adjusting the contact area to stabilize conduction filaments, and a method involving etching and deposition processes to form these structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the size of the memory cell is reduced to improve scalability, then device miniaturization is achieved, but the variation in the quantity of conduction filaments increases, affecting device reliability
Solution Approach 1:
The patent applies local quality by forming the resistance layer only in specific local regions defined by spacer structures on sidewalls of word lines, rather than uniformly across the entire device. This localized formation of resistance layers in controlled geometries ensures consistent contact areas between the resistance layer and electrodes, thereby stabilizing conduction filament formation even as device dimensions are reduced for scaling.
2Productivity
If the contact area between the resistance layer and electrode is reduced to enable further scaling, then device size decreases, but the stability of conduction filaments deteriorates
Solution Approach 1:
The patent transitions from planar contact geometry to three-dimensional contact structures by forming resistance layers on the sidewalls of word lines. This dimensional change creates well-defined contact areas through vertical spacer structures, allowing precise control of contact geometry in the vertical dimension while enabling horizontal scaling of the device footprint.
3Ease of manufacture
If conventional fabrication methods are used to simplify the manufacturing process, then ease of manufacture is maintained, but manufacturing precision and control over resistance layer geometry are insufficient
Solution Approach 1:
The patent employs preliminary action by first forming spacer structures on the sidewalls of word lines before depositing the resistance layer material. These pre-formed spacers serve as self-aligned masks and geometric templates, automatically defining the precise location, shape, and dimensions of the resistance layers. This preliminary structuring eliminates the need for complex subsequent patterning steps while ensuring high manufacturing precision.
Data Source
AI summary
A method of fabricating a resistive random access memory (RRAM) device is disclosed. A plurality of word lines extending along a first direction are formed on a substrate with a recess between the word lines. A spacer-type resistance layer and a top electrode layer are formed on a sidewall of each of the word lines. A photoresist stripe pattern extending along a second direction is then formed on the substrate. The first direction is perpendicular to the second direction. An etching process is performed to remove the top electrode layer and the spacer-type resistance layer not covered by the photoresist stripe pattern to form a plurality of top electrodes. A diode is formed on each of the top electrodes.