Low-Profile RRAM Structure Mitigating Step Height
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Solution Overview
Problem
As the pitch of interconnect layers in integrated circuits shrinks, filling the space between resistive random-access memory (RRAM) structures with dielectric materials becomes challenging, leading to defects like voids that can cause electrical shorts and compromise mechanical rigidity.
Innovation Solution
A method for forming RRAM structures with a low profile by creating a recess in the dielectric layer to expose sidewall surfaces of conductive structures, allowing the RRAM to wrap around these surfaces and reducing the height between RRAM and conductive structures, thereby facilitating the deposition of dielectric layers and minimizing void formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the pitch of interconnect layers is reduced to increase integration density, then the number of RRAM structures per area increases, but the space for dielectric material deposition between adjacent RRAM structures becomes insufficient leading to void formation
Solution Approach 1:
The RRAM structure transitions from a planar configuration to a three-dimensional configuration by wrapping around the sidewalls of conductive structures. This vertical dimensionality change allows the RRAM active area to extend onto the sidewalls, effectively increasing the functional area without increasing the lateral pitch, thereby maintaining adequate spacing for dielectric deposition while achieving higher integration density
Solution Approach 2:
The RRAM structure is nested around the conductive structure (via or line), with the resistive material and electrode layers conformally coating the sidewalls and top surface of the conductive structure. This nesting approach maximizes the use of available space in the vertical dimension while maintaining proper spacing between adjacent structures
2Device complexity
If the RRAM structure height is increased to accommodate additional functional layers, then the device complexity increases, but the space available for subsequent dielectric layer deposition is reduced
Solution Approach 1:
The RRAM structure exhibits local quality variations with different layer configurations at different locations: the bottom electrode layer is present on both the top surface and sidewalls of the conductive structure, while the resistive material layer is confined to the sidewalls. This localized differentiation allows the structure to achieve enhanced functionality without excessive overall height, facilitating subsequent dielectric deposition
3Productivity
If the space between adjacent RRAM structures is reduced to increase density, then the manufacturing precision requirements increase, but voids form during dielectric deposition
Solution Approach 1:
The RRAM structure is formed with a low profile configuration before subsequent dielectric layers are deposited. By completing the RRAM stack formation with controlled height and wrapping geometry beforehand, the structure creates adequate clearance for dielectric material to flow and fill the spaces between adjacent structures, preventing void formation while maintaining high density
Data Source
AI summary
The present disclosure is directed to a method for the formation of resistive random-access memory (RRAM) structures with a low profile between or within metallization layers. For example, the method includes forming, on a substrate, a first metallization layer with conductive structures and a first dielectric layer abutting sidewall surfaces of the conductive structures; etching a portion of the first dielectric layer to expose a portion of the sidewall surfaces of the conductive structures; depositing a memory stack on the first metallization layer, the exposed portion of the sidewall surfaces, and a top surface of the conductive structures; patterning the memory stack to form a memory structure that covers the exposed portion of the sidewall surfaces and the top surface of the conductive structures; depositing a second dielectric layer to encapsulate the memory stack; and forming a second metallization layer on the second dielectric layer.