RRAM High-K Layer Stepped Profile Prevents Electrode Shorts
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Solution Overview
Problem
Resistive random access memory (RRAM) devices face challenges in increasing density and preventing shorts between electrodes due to misalignment during the fabrication process, particularly in 3-D structures, where the lateral dimensions of the high-K layer and top electrode are typically equal, leading to potential short circuits.
Innovation Solution
A capping layer structure is implemented with a recess that includes a lower electrode and a high-K layer with a stepped profile, where the width of the high-K layer is greater than the lower electrode, decoupling the lateral dimensions and preventing shorts by increasing the distance between the top and bottom electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the lateral dimensions of the high-K layer and top electrode are made equal in 3-D RRAM structures, then the device density is increased, but the risk of short circuits between electrodes increases due to misalignment
Solution Approach 1:
The patent applies asymmetry by making the high-K layer wider than the bottom electrode, creating an asymmetric structure where the insulation layer extends beyond the electrode boundaries. This asymmetric design ensures that even with misalignment, the top electrode cannot contact the bottom electrode, preventing short circuits while maintaining high device density in 3-D RRAM structures.
2Manufacturing precision
If PVD is used to deposit RRAM stacks to control oxygen vacancy concentration, then the resistance control is improved, but the application to 3-D structures is prevented
Solution Approach 1:
The patent changes the deposition parameter from PVD to ALD (Atomic Layer Deposition). ALD allows precise control of oxygen vacancy concentration through controlled deposition conditions while being compatible with 3-D structures due to its conformal deposition capability. This parameter change enables both precise resistance control and 3-D structure fabrication.
Data Source
AI summary
A resistive random access memory (RRAM) device and a method for constructing the device is described. A capping layer structure is provided over a bottom contact where the capping layer includes a recess situated over the bottom contact. A first portion of the recess is filled with a lower electrode such that the width of the recess defines the width of the lower electrode. A second portion of the recess is filled with a high-K layer so that a bottom surface of the high-K layer has a stepped profile. A top electrode is formed on the high-K layer and a top contact is formed on the top electrode. The width of the high-K layer is greater than the width of the lower electrode to prevent shorting between the top contact and the lower electrode of the RRAM device.