RRAM Cell Layout That Avoids Switching Layer Etch Damage
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Solution Overview
Problem
Conventional resistive random access memory (RRAM) manufacturing processes, particularly dry etching, cause damage to the resistance switching layer, leading to unreliable and uncontrollable electrical resistance variations, which worsen with miniaturization, affecting the reliability and yield of RRAM devices.
Innovation Solution
A method for manufacturing RRAM that avoids dry etching of the resistance switching layer by forming it conformally within trenches and openings, ensuring the top surfaces of all layers are coplanar, reducing damage and enabling horizontal memory cell configuration, thereby increasing density and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If dry etching process is used to define memory cells, then memory cell patterning is achieved, but damage to the resistance switching layer occurs
Solution Approach 1:
The patent segments the etching process into two distinct stages: first etching trenches to a first depth without penetrating the resistance switching layer, then subsequently etching openings to a second depth that penetrates through the resistance switching layer. This segmentation prevents the harmful effects of deep etching from affecting the resistance switching layer while still achieving the required memory cell patterning.
Solution Approach 2:
The patent performs preliminary trench etching to a controlled first depth before forming the resistance switching layer, ensuring that the subsequent opening etching can penetrate through the resistance switching layer without requiring excessive etching depth that would cause damage. This preliminary action establishes a foundation that protects the resistance switching layer from damage.
2Area of moving object
If memory cell critical dimension is reduced for miniaturization, then device density increases, but damage from etching process becomes more significant
Solution Approach 1:
The patent transitions from controlling memory cell dimensions solely in the lateral plane to utilizing the vertical dimension by implementing a two-stage etching process with distinct depths. This dimensional approach allows for scaled-down memory cell areas while maintaining protection of the resistance switching layer by controlling the vertical penetration depth of the first etching stage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces damage to the resistance switching layer, enhancing the reliability and yield of RRAM while facilitating miniaturization by eliminating uncontrollable damage regions and allowing for increased memory cell density.
Implementation Method 1
a resistance switching layer conformally formed on a surface of an opening located between the two trenches
Data Source
AI summary
A RRAM and its manufacturing method are provided. The RRAM includes a first dielectric layer formed on a substrate, and two memory cells. The two memory cells include two bottom electrode structures separated from each other. Each bottom electrode structure fills one of two trenches in the first dielectric layer. The two memory cells also include a resistance switching layer and a top electrode structure. The resistance switching layer is conformity formed on the surface of an opening in the first dielectric layer, and the opening is between the two trenches. The top electrode structure is on the resistance switching layer and fills the opening. A top surface of the first dielectric layer, top surfaces of the bottom electrode structures, a top surface of the resistance switching layer, and a top surface of the top electrode structure are coplanar.