Temporal Memory Hardware Using RRAM Crossbar Arrays
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Solution Overview
Problem
Current temporal memory systems lack efficient hardware implementations for pattern identification and prediction based on continuous input streams, particularly in neuromorphic chips, and existing hardware implementations do not effectively utilize non-volatile memory elements to mimic synaptic connections between temporal contexts.
Innovation Solution
A hardware implementation of a temporal memory system using non-volatile memory cells, such as RRAM elements, to store the likelihood of sequence occurrences and mimic synaptic connections, enabling pattern identification and prediction by representing temporal coincidence between input frames through a crossbar array and buffering unit for efficient processing and prediction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If non-volatile memory cells are used to store temporal patterns and mimic synaptic connections, then pattern identification and prediction capability is improved, but device complexity increases
Solution Approach 1:
The patent replaces traditional volatile memory and software-based temporal processing with non-volatile memory cells that inherently maintain temporal patterns through their physical state. The NVM elements naturally mimic synaptic connections through adjustable resistance states, eliminating the need for complex software algorithms to implement temporal memory functions.
Solution Approach 2:
The invention utilizes the adjustable resistance parameter of non-volatile memory elements to encode temporal relationship strengths. By changing the resistance values of NVM cells based on observed temporal coincidences, the system dynamically adapts its pattern recognition capabilities without requiring complex control logic.
2Use of energy by moving object
If RRAM elements are used to mimic synaptic connections and store sequence likelihoods, then power consumption is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The non-volatile memory elements automatically maintain their stored temporal patterns without requiring continuous power supply or refresh operations. The NVM cells self-preserve the sequence likelihood information through their non-volatile nature, eliminating the power consumption associated with volatile memory refresh cycles.
Solution Approach 2:
The system compensates for manufacturing variations in RRAM elements by using adjustable resistance values that can be tuned during operation. The temporal pattern storage utilizes the continuous resistance spectrum of NVM elements, allowing precise encoding of sequence likelihoods despite initial fabrication tolerances.
3Productivity
If temporal coincidence between input frames is represented through crossbar array, then prediction efficiency is improved, but device complexity increases
Solution Approach 1:
The patent divides the temporal memory function into discrete segments corresponding to individual non-volatile memory cells, each representing a specific temporal relationship. The crossbar array is segmented into rows and columns that correspond to different input frames and temporal contexts, allowing parallel processing of multiple temporal relationships simultaneously.
Solution Approach 2:
The crossbar array structure serves multiple functions: it stores temporal patterns, performs pattern matching, and generates predictions all through the same hardware infrastructure. The NVM elements in the crossbar array universally handle both storage and computation tasks, eliminating the need for separate memory and processing units.
Data Source
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AI summary
A hardware implementation of a temporal memory system (10) comprises - at least one array (360, 361, 362) of memory cells (40) logically organized in rows and columns, each memory cell being adapted for storing a scalar value and adapted for changing, e.g. for incrementing or decrementing, the stored scalar value, - an input system (340) adapted for receiving an input frame as input and for creating a representation for that input, which is fit for memory cell addressing in the at least one array, - at least one addressing unit for identifying a memory cell in the at least one array with a row address and a column address, the at least one addressing unit comprising - a column addressing unit (41) for receiving the representation or a derivative thereof as input and applying the representation or the derivative as a column address to the array of cells, and - a row addressing unit (42) for receiving a delayed version of the representation at a specified time in the past as input, and applying this representation as a row address to the array of cells, - a reading unit (43) adapted for reading out scalar values from a selected row of memory cells in the array, based on the row address applied, each read out scalar value corresponding to a likelihood of temporal coincidence between the input representation of the row address and the input representation of the column address, this likelihood being adjustable through the scalar value stored in the memory cell.