RRAM Two-Step Read Using Cell-Specific Reference Values
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Solution Overview
Problem
Existing MRAM technologies face challenges in reading codewords with high bit error rates due to variations in resistance values among memory cells, leading to inefficiencies in read operations and potential write errors, especially when using self-referenced reads.
Innovation Solution
A two-step read process is employed, utilizing a global read reference value followed by an individual read reference value retrieved from a lookup table, minimizing bit errors and reducing the need for self-referenced reads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single global read reference value is used for all memory cells, then the read operation is simple and fast, but bit error rates increase due to resistance variations among memory cells
Solution Approach 1:
The patent segments the read reference value selection into two levels: a global read reference value applied to all memory cells for fast initial reads, and individual read reference values stored in a lookup table for specific memory cells that require error correction. This segmentation allows the system to maintain fast read operations while providing targeted precision for problematic cells.
Solution Approach 2:
The patent changes the read reference value parameter dynamically based on the specific memory cell being read. Instead of using a fixed global reference value, the system retrieves cell-specific reference values from a lookup table when bit errors are detected, allowing optimization of the read operation for each individual cell's resistance characteristics.
2Reliability
If self-referenced reads are used to correct bit errors, then read reliability improves, but write errors increase and endurance decreases
Solution Approach 1:
The patent performs preliminary characterization of each memory cell's resistance properties during manufacturing or initialization, storing optimal read reference values in a lookup table before actual read operations begin. This preliminary action eliminates the need for repeated self-referenced reads during normal operation, thereby reducing wear and extending memory endurance while maintaining high read reliability.
3Reliability
If individual read reference values are stored for each memory cell, then bit error rates decrease, but device complexity and memory overhead increase
Solution Approach 1:
The patent applies partial individualization by storing read reference values only for memory cells that exhibit resistance variations causing bit errors, rather than maintaining individual reference values for all cells. The lookup table contains entries only where needed, allowing the system to achieve error correction benefits while minimizing the overhead and complexity associated with storing individual reference values.
Data Source
AI summary
An apparatus is provided that includes a memory array and a control circuit. The memory array includes non-volatile memory cells each including a resistive random access memory element. The control circuit is configured to receive a read command that specifies an address of a first group of the non-volatile memory cells, use a first predetermined read reference value to perform a first read of the first group of the non-volatile memory cells to provide first read data, while performing the first read, retrieve from a memory a second predetermined read reference value corresponding to the specified address, and in response to a condition being satisfied regarding the first read data, use the second predetermined read reference value to perform a second read of the first group of the non-volatile memory cells to provide second read data.