Two-Step Reset Technique for RRAM Memory Window Expansion
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Solution Overview
Problem
As RRAM cells scale down, their performance and reliability degrade, leading to a reduced memory window, making it difficult to accurately read data states due to decreased distinguishability between high and low resistive states.
Innovation Solution
A two-step reset operation is performed on RRAM cells, where a first reset voltage with a specific polarity changes the cell from a low to an intermediate resistive state, and a second reset voltage with an opposite polarity further increases the resistive state, resulting in a larger memory window without altering the cell design or operation time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If RRAM cells are scaled down to reduce cell area, then device integration density is improved, but memory window is reduced making data states harder to distinguish
Solution Approach 1:
The reset operation is divided into two distinct steps: a first reset step that transitions the cell from low resistive state to intermediate resistive state, and a second reset step that transitions from intermediate to high resistive state. This segmentation of the reset operation enables progressive resistance modulation, allowing the memory window to be maintained or enhanced even as cell dimensions are scaled down.
Solution Approach 2:
The patent utilizes dynamic changes in voltage polarity and magnitude across the two reset steps. The first reset voltage has a first polarity and transitions resistance partially, while the second reset voltage has an opposite polarity and completes the transition to high resistance. This parameter modulation approach allows precise control over the resistive states, maintaining distinguishability between data states despite cell scaling.
2Speed
If a single-step reset operation is used, then operation speed is maintained, but memory window is insufficient for reliable data reading
Solution Approach 1:
The reset operation employs periodic voltage pulses with alternating polarities. The first reset voltage pulse transitions the cell to an intermediate state, and the second reset voltage pulse with opposite polarity completes the transition to the high resistive state. This periodic action pattern enables the two-step reset process to achieve both speed and sufficient memory window for reliable data reading.
3Measurement precision
If reset voltage magnitude is increased to enlarge memory window, then data state distinguishability is improved, but energy consumption increases
Solution Approach 1:
The first reset voltage applies a partial reset action that transitions the cell to an intermediate resistive state rather than directly to the final high resistance state. The second reset voltage then completes the transition. This partial action approach distributes the energy requirement across two steps, achieving the desired memory window while managing overall energy consumption more effectively than a single high-voltage pulse would require.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The two-step reset operation enhances the memory window of RRAM cells, improving data read reliability by increasing the difference between high and low resistive states, thus better distinguishing between data values.
Implementation Method 1
applying a first reset voltage to an RRAM cell having a first polarity to change the RRAM cell from a low resistance to an intermediate resistance
Implementation Method 2
applying a second reset voltage to the RRAM cell, wherein the second polarity is opposite to the first polarity, to induce the RRAM cell to have a high resistance
Data Source
AI summary
In some embodiments, the present disclosure relates to a method, comprising the performing of a reset operation to a resistive random access memory (RRAM) cell. A first voltage bias having a first polarity is applied to the RRAM cell. An absolute value of the first voltage bias is greater than an absolute value of a first reset voltage. The application of the first voltage bias induces the RRAM cell to change from a low resistance to an intermediate resistance greater than the low resistance. A second voltage bias having a second polarity oppose to the first polarity is then applied to the RRAM cell. An absolute value of the second reset voltage is less than an absolute value of the second voltage bias and less than the absolute value of the first reset voltage. The application of the second voltage bias induces the RRAM cell to have a high resistance.