Universal RRAM Dielectric Layer for Multi-Application Memory Integration
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Solution Overview
Problem
Conventional RRAM devices require multiple recipes to form variable resistance dielectric layers with different thicknesses and crystalline structures for various applications, leading to increased time and cost in fabricating RRAM devices suitable for multiple applications on a single chip.
Innovation Solution
A novel RRAM architecture that uses a single recipe to form a universal variable resistance dielectric layer, allowing multiple RRAM macros on a single chip to be used in different applications by applying distinct signal levels, thereby eliminating the need for multiple recipes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple recipes are used to form variable resistance dielectric layers with different thicknesses and crystalline structures for various applications, then the RRAM devices can achieve suitable endurance levels for different applications, but the fabrication time and cost increase
Solution Approach 1:
The patent applies universality by creating a single variable resistance dielectric layer that can serve multiple applications (eFuse, MTP, data storage) with different endurance requirements. The layer is designed to be universally applicable across different RRAM macros on the same chip, eliminating the need for separate layers for each application type.
Solution Approach 2:
The patent applies local quality by configuring different RRAM macros to operate at different signal levels (voltage thresholds) within the same dielectric layer. Each macro is tuned to have distinct read and write voltage thresholds, allowing differentiation of applications locally within the unified layer structure without requiring multiple fabrication recipes.
2Reliability
If multiple recipes are used to form variable resistance dielectric layers with different thicknesses and crystalline structures for various applications, then the RRAM devices can achieve suitable endurance levels for different applications, but the fabrication cost increases
Solution Approach 1:
The patent reduces fabrication cost by implementing a universal variable resistance dielectric layer that serves all RRAM macros regardless of their specific application. This single-layer approach eliminates the need for multiple deposition and annealing processes that would be required to create separate dielectric layers with different properties for eFuse, MTP, and data storage applications.
Solution Approach 2:
The patent changes operational parameters (signal levels, voltage thresholds) rather than physical parameters (thickness, crystalline structure) to differentiate between applications. By tuning the voltage thresholds at which different macros operate, the system achieves application-specific performance without requiring multiple fabrication recipes, thereby reducing manufacturing complexity and cost.
3Productivity
If a single recipe is used to form a universal variable resistance dielectric layer, then the fabrication time and cost are reduced, but it must accommodate multiple applications with different endurance requirements
Solution Approach 1:
The patent achieves application-specific configuration within a unified layer by implementing local quality through distinct voltage threshold settings for each RRAM macro. Each macro is designed with specific read and write voltage thresholds that allow it to be selectively activated or deactivated based on the desired application, enabling eFuse, MTP, and data storage functions from the same dielectric layer.
Solution Approach 2:
The patent creates a multi-functional system where a single variable resistance dielectric layer supports multiple applications simultaneously. The unified layer structure is designed to be universally configurable, allowing different RRAM macros to be tuned for different purposes through voltage threshold control rather than requiring separate physical layers for each application type.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the integration of multiple RRAM macros for various applications on a single chip without additional fabrication time or cost, while maintaining suitable endurance levels for each application.
Implementation Method 1
Resistive random-access memory (RRAM) devices are non-volatile memory type devices formed using semiconductor manufacturing methods. Generally, RRAM devices operate under the principle that a dielectric, which is normally insulating, can be made to conduct through a filament or conduction path formed after the application of a sufficiently high voltage.
Implementation Method 2
The conduction path formation can arise from different mechanisms, including but not limited to defect, metal migration, oxygen vacancy, etc.
Implementation Method 3
The conduction path formation can arise from different mechanisms, including but not limited to defect, metal migration, oxygen vacancy, etc.
Data Source
AI summary
A memory architecture includes: a first memory macro comprising a first plurality of memory cells that each comprises a first variable resistance dielectric layer with a first geometry parameter; and a second memory macro comprising a second plurality of memory cells that each comprises a second variable resistance dielectric layer with a second geometry parameter, wherein the first geometry parameter is different from the second geometry parameter thereby causing the first and second memory macros to have first and second endurances. The first and second variable resistance dielectric layers are formed using a single process recipe. The first endurance comprises a maximum number of cycles for which the first plurality of memory cells can transition between first and second logical states, and the second endurance comprises a maximum number of cycles for which the second plurality of memory cells can transition between the first and second logical states.