Variable Pulse Write Read Methods for RRAM Memory Cells
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Solution Overview
Problem
Resistive random access memory (RRAM) devices face challenges in write and read operations due to wide distribution of write pulses and cell resistance, making it difficult to achieve reliable data writing and reading.
Innovation Solution
A variable write method for RRAM and spin-transfer torque random access memory (STRAM) that involves applying multiple write or read pulses with increasing durations until the desired resistance state is achieved, within the transistor's current driving capability, to enhance writability and readability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple write pulses with increasing durations are applied to RRAM cells, then the writability and reliability of data writing is improved, but the write time and operation duration increases
Solution Approach 1:
The write pulse duration is made dynamic rather than fixed. The method applies a sequence of write pulses with progressively increasing durations (e.g., 100ps, 200ps, 300ps, etc.) to accommodate the wide distribution of switching characteristics in RRAM cells. This dynamic adjustment ensures that each cell receives the minimum necessary pulse duration to switch reliably, improving overall writability while minimizing unnecessary write time for cells that switch faster.
Solution Approach 2:
The write operation uses periodic pulsed action instead of a continuous signal. Multiple discrete write pulses are applied in sequence with increasing durations, allowing the system to systematically probe and accommodate the varying switching thresholds of different RRAM cells. This periodic approach enables reliable writing across the distribution of cell characteristics.
2Reliability
If the write pulse duration is increased to accommodate cells with higher switching currents, then the reliability of writing is improved, but the write speed decreases
Solution Approach 1:
The write pulse duration is dynamically adjusted based on the specific cell's switching characteristics. Instead of using a uniformly long pulse for all cells, the method applies progressively longer pulses only until switching is achieved. This dynamic approach ensures that cells with lower switching thresholds switch faster, while cells with higher thresholds receive the additional time they need, optimizing both speed and reliability.
Solution Approach 2:
The write pulse parameters (specifically duration) are changed systematically to match the distribution of switching currents in the RRAM array. By varying the pulse duration parameter across a range of values (100ps to several nanoseconds), the system adapts to the wide variation in cell characteristics, achieving reliable switching without unnecessarily extending write time for all cells.
3Reliability
If multiple read pulses with increasing durations are applied to STRAM cells, then the readability is improved, but the read time increases
Solution Approach 1:
The read pulse duration is made dynamic to accommodate variations in STRAM cell switching characteristics. The method applies a sequence of read pulses with increasing durations to cells that fail to switch on previous attempts. This dynamic adjustment ensures that the read operation successfully completes for all cells in the array, improving overall readability while minimizing the time impact on cells that read successfully on the first attempt.
Solution Approach 2:
The read operation incorporates feedback by monitoring whether each cell has successfully switched after each read pulse. Based on this feedback, the system determines whether to apply additional read pulses with longer durations. This feedback mechanism ensures that read time is extended only for cells that require it, rather than uniformly increasing read time for the entire array.
4Ease of operation
If the distribution of write pulse and cell resistance is narrowed, then the difficulty of writing and reading is reduced, but the adaptability to varying cell characteristics decreases
Solution Approach 1:
The system deliberately uses a wide range of write pulse parameters ( durations from 100ps to several nanoseconds) to adapt to the wide distribution of cell resistance and switching characteristics in RRAM arrays. This parameter variation approach maintains high adaptability to cell variation while the systematic progression of pulse durations provides ease of operation by automatically accommodating different cell types without manual intervention.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the reliability and speed of writing and reading operations in RRAM and STRAM by ensuring that memory cells are written or read successfully without exceeding the transistor's current limit, thereby enhancing the overall performance of these memory devices.
Implementation Method 1
The variable resistive material layer, i.e., a data storage material layer, has a reversible variation in resistance according to the whether a filament, a conductive path or a low resistive path is formed through the resistive material layer by the electrical signal (voltage or current) applied between the electrodes
Implementation Method 2
A new write mechanism, which is based upon spin polarization current induced magnetization switching, has been introduced to the RRAM design
Data Source
AI summary
Variable write and read methods for resistance random access memory (RRAM) are disclosed. The methods include initializing a write sequence and verifying the resistance state of the RRAM cell. If a write pulse is needed, then two or more write pulses are applied through the RRAM cell to write the desired data state to the RRAM cell. Each subsequent write pulse has substantially the same or greater write pulse duration. Subsequent write pulses are applied to the RRAM cell until the RRAM cell is in the desired data state or until a predetermined number of write pulses have been applied to the RRAM cell. A read method is also disclosed where subsequent read pulses are applied through the RRAM cell until the read is successful or until a predetermined number of read pulses have been applied to the RRAM cell.