3D RRAM Vertical Stacking for CMOS Integration
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Solution Overview
Problem
Current 3D resistive random access memory (RRAM) manufacturing processes require deep etching and filling, making it difficult to integrate with advanced logic processes like CMOS.
Innovation Solution
A resistive random access memory design with vertically adjacent memory cells and isolated variable resistance structures, connected by second vias, which eliminates the need for deep etching and filling, allowing direct integration with advanced logic processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If deep etching and filling processes are used to manufacture 3D RRAM, then memory density is improved, but integration with advanced logic processes becomes difficult
Solution Approach 1:
The patent transitions from planar 2D memory cell arrangement to vertical 3D stacking architecture. Multiple memory cells are stacked vertically along the Z-axis, with each cell occupying a different height level. This dimensional change enables higher memory density within the same footprint while using standard shallow etching and filling processes compatible with advanced CMOS logic manufacturing.
2Quantity of substance
If vertical stacking of memory cells is implemented, then memory density is improved, but process complexity increases
Solution Approach 1:
The vertical stack is segmented into discrete memory cells, each with its own first via, conductive lines, and variable resistance structures. The stack is further divided into multiple levels separated by intermediate dielectric layers. This segmentation allows each cell to be independently formed using standard processes while achieving high density through vertical integration.
Solution Approach 2:
Multiple memory cells are nested vertically within each other, with each cell containing vias and conductive structures that are positioned at different vertical levels. The nested arrangement allows efficient use of vertical space while maintaining electrical isolation between cells through dielectric layers, reducing overall device complexity compared to lateral expansion.
3Reliability
If variable resistance structures are isolated between vertically adjacent memory cells, then cross-talk is reduced, but manufacturing precision requirements increase
Solution Approach 1:
Intermediate dielectric layers are introduced between vertically adjacent memory cells to provide electrical isolation and prevent cross-talk. These dielectric layers act as mediators that physically separate the variable resistance structures of different cells while maintaining the vertical stacking architecture. The dielectric material provides both insulation and structural support, reducing the precision requirements for direct alignment of conductive structures.
Data Source
AI summary
A resistive random access memory including a substrate, a dielectric layer disposed on the substrate and at least one memory cell string is provided. The memory cell string includes memory cells and second vias. The memory cells are vertically and adjacently disposed in the dielectric layer, and each of the memory cells includes a first via, two conductive lines respectively disposed at two sides of the first via and two variable resistance structures respectively disposed between the first via and the conductive lines. In the vertically adjacent two memory cells, the variable resistance structures of the upper memory cell and the variable resistance structures of the lower memory cell are isolated from each other. The second vias are respectively disposed in the dielectric layer under the first vias and connected to the first vias, and the vertically adjacent two first vias are connected by the second via.