3D RRAM Bit Cell Integration via Vertical Stacking

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Solution Overview

Problem

Existing RRAM devices are limited in the number of bit cells that can be integrated within a given area, as they can only be integrated two-dimensionally, restricting their density and performance.

Innovation Solution

The integration of RRAM bit cells is enhanced by forming a three-dimensional structure, where subsets are integrated vertically and further integrated laterally through common electrode contacts and horizontal electrode contacts, allowing for increased density without altering existing CMOS technology processing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If RRAM devices are integrated in a traditional two-dimensional stack configuration, then the fabrication process is simple, but the number of RRAM devices that can be integrated within a given area is limited

Engineering Contradiction:

Improvenumber of RRAM devicesVSAvoidintegration area

Core Design Contradiction:

Quantity of substanceVSArea of stationary object

Solution Approach 1:

The patent transitions from two-dimensional integration to three-dimensional integration by forming RRAM devices in a vertical stack configuration. Multiple RRAM devices are stacked vertically along a common first electrode contact, enabling significantly higher integration density within the same footprint area while maintaining compatibility with existing CMOS fabrication processes

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Quantity of substance

If more RRAM devices are integrated to increase IC power, then the device density improves, but the fabrication complexity increases

Engineering Contradiction:

Improvenumber of RRAM devicesVSAvoidfabrication process complexity

Core Design Contradiction:

Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent segments the RRAM device structure into modular components including a common first electrode contact shared by multiple devices, individual second electrode contacts, and variable resistive material layers. This segmentation allows for systematic fabrication through repeated deposition and patterning cycles while sharing common structural elements, thereby managing fabrication complexity

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The first electrode contact serves as a common electrode for multiple RRAM devices stacked vertically, performing the dual function of being both an electrode for each individual device and a shared interconnect structure. This multi-functionality reduces the total number of electrodes required and simplifies the overall fabrication process

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS11158790B2Resistive random access memory device

Publication Date: 2021.10.26 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A memory cell includes: a first electrode contact formed as a cylinder shape that extends along a first direction; a resistive material layer comprising a first portion that extends along the first direction and surrounds the first electrode contact; and a second electrode contact coupled to the resistive material layer, wherein the second electrode contact surrounds the first electrode contact and the first portion of the resistive material layer.