RRAM Write Verify Circuit Using Dynamic Bit Line Voltage Ramp
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Solution Overview
Problem
Conventional resistive random access memory (RRAM) writing and verifying methods face challenges in controlling the writing and verifying timing period due to poorly defined bit line voltage, leading to inefficient writing operations and reduced performance.
Innovation Solution
A method and circuit that continuously decrease the bit line voltage from a first to a second voltage level during the writing and verifying timing period, using a diode to generate an exponentially varying reference current for precise detection of the finish time point by comparing it with the detected current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a constant bias voltage is applied to the bit line during the writing and verifying timing period, then the circuit operation is simplified, but the writing operation time becomes too large and performance is reduced
Solution Approach 1:
The patent applies dynamics by transitioning from a static constant bias voltage to a dynamic ramp voltage that continuously increases during the writing and verifying timing period. This dynamic voltage application allows the bit line voltage to adapt to the changing resistance states during the writing operation, enabling faster convergence to the target current level and reducing the overall operation time while maintaining circuit simplicity.
2Ease of operation
If a constant bias voltage is applied to the bit line during the writing and verifying timing period, then the voltage control is simplified, but the cycles of the writing and verifying timing period are hard to be controlled
Solution Approach 1:
The ramp voltage dynamically adjusts the bit line voltage throughout the timing period, enabling precise control of the writing and verifying cycles. The continuous voltage increase ensures that the operation completes within a defined time window, improving timing control precision while keeping the voltage control mechanism relatively simple through a single ramp signal.
Solution Approach 2:
The patent employs feedback by detecting the bit line current and comparing it with a target current to determine when the writing operation is complete. This feedback mechanism, combined with the ramp voltage, allows precise control of the timing period cycles by automatically terminating the operation when the target state is reached, thereby reducing unnecessary time loss.
3Device complexity
If a constant bit line voltage is applied during the writing and verifying timing period, then the verification process is simplified, but the performance of the writing operation is reduced
Solution Approach 1:
The ramp voltage enhances writing operation performance by dynamically increasing the bit line voltage during the timing period. This dynamic approach accelerates the writing process and improves verification efficiency by ensuring that the voltage is optimally adjusted throughout the operation, thereby boosting overall productivity without significantly complicating the verification process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for more precise and efficient completion of the writing and verifying operation, improving the performance of RRAM by accurately determining the finish time point of the writing and verifying timing period.
Implementation Method 1
a diode and is configured to apply the bit line voltage to the cathode of the diode providing an exponential variation of the reference current (CREF) with the bit line voltage (VVER)
Data Source
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AI summary
A writing and verifying circuit and a method for writing and verifying a resistive memory thereof are provided. The steps of the method includes: enabling one word line signal corresponding to one selected resistive memory cell of the resistive memory during a writing and verifying timing period; providing a bit line voltage to the selected resistive memory cells, wherein the bit line voltage continuously increases or decreases from a first voltage level to a second voltage level during the writing and verifying timing period; and, measuring a detected current through the bit line and determining a finish time point of the writing and verifying timing period according to the detected current and a reference current.