RRAM Write-Back Circuit Prevents Leakage
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Solution Overview
Problem
Resistive random-access memory (RRAM) devices face challenges in miniaturization due to the need for transistor size to maintain cross voltage, leading to large device areas, and current leakage issues without transistors, which complicates the transition of resistance states during read operations.
Innovation Solution
The implementation of a write-back mechanism in RRAM devices, involving a memory array, read circuit, write-back circuit, and write-back logic circuit, which changes the resistance state of selected memory cells from a low to a high resistance state after reading, preventing current leakage and maintaining data integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a transistor is used in the memory cell to block current leakage, then current leakage is prevented, but the device area increases due to the transistor size requirement for maintaining cross voltage
Solution Approach 1:
The patent extracts the transistor from the memory cell structure, transitioning from 1T1R to 0T1R or 0T2R configurations. This removal eliminates the current leakage blocking function of the transistor while reducing the device area, as the cross voltage maintenance is achieved through other means in the memory cell design
Solution Approach 2:
The patent implements a write-back mechanism that serves multiple functions: it restores the resistance state of memory cells after read operations, prevents current leakage in unselected cells, and maintains data integrity. This single mechanism replaces the need for transistors in blocking current leakage
2Area of stationary object
If the transistor size is reduced to minimize device area, then device area decreases, but the cross voltage of the memory cell is affected
Solution Approach 1:
The patent changes the operational parameters of the memory cell by implementing write-back mechanisms with specific voltage levels and timing sequences. The write-back circuit applies controlled voltages to restore resistance states, ensuring cross voltage maintenance without requiring large transistors
Solution Approach 2:
The patent introduces a write-back circuit as an intermediary component that mediates between the read operation and the memory cell state. This circuit actively restores the resistance state of memory cells after reading, ensuring proper cross voltage levels are maintained without relying on large transistor sizes
3Area of stationary object
If no transistor is used in the memory cell, then device area is reduced enabling miniaturization, but current leakage occurs from selected to unselected memory cells
Solution Approach 1:
The patent implements a continuous write-back mechanism that actively restores memory cell states after read operations. This continuous action prevents current leakage by ensuring unselected memory cells return to their proper resistance states, compensating for the lack of transistor-based blocking
Solution Approach 2:
The patent employs feedback mechanisms where the read circuit detects the state of memory cells and triggers write-back operations when needed. The write-back logic circuit monitors read operations and activates the write-back circuit to prevent current leakage, creating a closed-loop system that maintains memory integrity without transistors
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables effective miniaturization of RRAM devices by preventing current leakage and ensuring accurate data storage and retrieval, enhancing operational reliability and reducing device area.
Implementation Method 1
the write-back circuit performs a write-back operation on the selected memory cell according to a write-back control signal and a write-back voltage, so as to change a resistance state of the selected memory cell from a low resistance state to a high resistance state
Data Source
AI summary
A resistive random-access memory device includes a memory array, a read circuit, a write-back logic circuit and a write-back circuit. The read circuit reads the data stored in a selected memory cell and accordingly generates a first control signal. The write-back logic circuit generates a write-back control signal according to the first control signal and a second control signal. The write-back circuit performs a write-back operation on the selected memory cell according to the write-back control signal and a write-back voltage, so as to change a resistance state of the selected memory cell from a low resistance state to a high resistance state, and generates the second control signal according to the resistance state of the selected memory cell.