RRAM Convolutional Block Using Complementary XNOR Amplifiers
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Solution Overview
Problem
Convolutional blocks in image processing and machine learning, particularly in convolutional neural networks, face high processing costs and power consumption issues, making them unsuitable for smaller devices, and existing solutions using hardware accelerators or resistive random access memories (RRAMs) either increase power consumption or introduce accuracy errors due to device variability.
Innovation Solution
A resistive random-access memory (RRAM)-based convolutional block utilizing a complementary pair of RRAMs and a programming circuit to program the RRAMs into low or high resistive states based on kernel bits, combined with an XNOR sense amplifier circuit to perform XNOR operations, reducing processing cost and energy consumption while addressing RRAM process variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If hardware accelerators are used to increase convolution processing speed, then processing speed is improved, but power consumption and processing complexity increase
Solution Approach 1:
The patent replaces traditional CMOS-based digital computing mechanisms with RRAM-based computing mechanisms. The RRAM devices perform XNOR operations through their inherent resistive switching behavior, eliminating the need for complex CMOS logic circuits and reducing power consumption while maintaining processing speed.
Solution Approach 2:
The patent changes the operational parameters by using binary-weighted RRAM devices where the resistance state directly encodes the kernel weight values. This parameter change allows the system to perform convolution operations through simple voltage division and current measurement, dramatically reducing computational complexity and power consumption compared to traditional floating-point arithmetic.
2Area of stationary object
If RRAMs are used to perform analog dot product, then area is reduced, but device variability introduces accuracy errors
Solution Approach 1:
The patent segments the kernel weights into binary-weighted values stored in RRAM devices, with each RRAM cell representing a specific weight bit. This segmentation allows the system to perform parallel XNOR operations for each bit position, accumulating results through simple addition while maintaining accuracy despite RRAM variability.
Solution Approach 2:
The patent uses complementary RRAM pairs where one RRAM stores the inverse of the other, creating redundant copies of the weight information. This copying strategy allows error detection and correction mechanisms to compensate for device variability, maintaining computational accuracy while using compact RRAM structures.
3Use of energy by moving object
If binary RRAM operations are used to improve energy efficiency, then energy consumption is reduced, but offset voltage causes operational failure
Solution Approach 1:
The patent employs asymmetric readout circuitry specifically designed to compensate for the inherent offset voltage in RRAM devices. The readout amplifier uses asymmetric feedback paths that dynamically balance the offset voltage, allowing reliable binary operation of RRAM devices while maintaining low power consumption.
Solution Approach 2:
The patent implements feedback mechanisms in the readout circuit where the output is fed back through adjustable resistors to dynamically cancel offset voltage. This feedback loop continuously adapts to RRAM device variations, ensuring operational reliability while maintaining the energy efficiency benefits of binary RRAM operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The RRAM-based convolutional block achieves significant energy savings, improved robustness, and accuracy, with up to 48% energy savings over CMOS XNOR implementations and 100% reliability under certain RRAM variability conditions, making it suitable for smaller devices.
Implementation Method 1
program the first RRAM to at least one selected from a group consisting of a low resistive state and a high resistive state, based on the kernel bit
Implementation Method 2
perform a XNOR operation between the input bit and the kernel bit read from the complementary pair of RRAMs
Data Source
AI summary
One embodiment provides a resistive random-access memory (RRAM) based convolutional block including a complementary pair of RRAMs having a first RRAM and a second RRAM, a programming circuit coupled to the complementary pair of RRAMs, and a XNOR sense amplifier circuit coupled to the complementary pair of RRAMs. The programming circuit is configured to receive a kernel bit from a kernel matrix, program the first RRAM to at least one selected from a group consisting of a low resistive state (LRS) and a high resistive state (HRS) based on the kernel bit, and program the second RRAM to other of the LRS and the HRS. The XNOR sense amplifier circuit is configured to receive an input bit from an input matrix, perform a XNOR operation between the input bit and the kernel bit read from the complementary pair of RRAMs, and output a XNOR output based on the XNOR operation.