RRAM Cell Circuit for In-Memory XNOR and Threshold Readout
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Solution Overview
Problem
Existing neuromorphic circuits for binary neural networks face challenges with excessive variability of resistive memory cells, leading to limited operands in MAC operations, complex circuitry for threshold comparisons, and significant surface area and power consumption, while existing solutions are either limited to 9 inputs or require complex comparators.
Innovation Solution
An electronic circuit design utilizing a 4T4R or 2T2R memristive memory cell structure with differential encoding of weights, performing XNOR operations directly between inputs and synaptic weights, and using a read module to determine the resulting value from the source line voltage, reducing complexity and variability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If RRAM-based neuromorphic circuits are used to implement binary neural networks, then computing speed and energy efficiency are improved, but device variability increases and manufacturing precision deteriorates
Solution Approach 1:
The patent applies parameter changes by utilizing the resistance state of memristors to encode binary weights (0 or 1) and by adjusting voltage levels on word lines and bit lines to perform XNOR operations. The memristor resistance can be switched between high and low states through applied voltage, enabling binary weight storage and computation without requiring precise manufacturing tolerances
Solution Approach 2:
The patent replaces traditional CMOS-based logic operations with memristor-based resistive operations. Instead of using transistors and complex logic gates to perform XNOR operations, the invention uses the natural resistive properties of memristors combined with simple transistor switches to achieve the same computational function with reduced variability impact
2Manufacturing precision
If conventional CMOS technology is used for neurons and synapses, then manufacturing precision is maintained, but device area increases and integration density decreases
Solution Approach 1:
The patent merges memory and computation functions into a single integrated structure. Memristors store weights while simultaneously participating in MAC operations through resistive division, eliminating the need for separate memory and compute units. This compute-in-memory approach reduces the overall chip area by combining functions that were previously implemented as separate components
Solution Approach 2:
The patent uses a matrix arrangement where memory cells are organized in rows and columns, with each cell representing a synaptic weight. This regular, replicated structure allows for efficient parallel processing and reduces the area required per neuron compared to conventional CMOS implementations that require dedicated transistors for each computational element
3Area of stationary object
If RRAM cells with high variability are used, then device area is reduced, but circuit complexity increases due to threshold comparison requirements
Solution Approach 1:
The patent extracts the threshold comparison function from complex comparator circuits and embeds it directly into the memory cell structure itself. By using the inherent resistance characteristics of memristors and applying appropriate voltages to bit lines, the threshold comparison is performed naturally during the read operation, eliminating the need for external comparator circuits
Solution Approach 2:
The patent implements self-service by allowing the memristor array to perform computations autonomously through resistive division during read operations. The voltage division that occurs when reading from the memory array naturally produces output voltages that encode the result of MAC operations, eliminating the need for external computation circuits and reducing overall system complexity
4Measurement precision
If complex comparator circuits are added to handle RRAM variability, then measurement precision is improved, but power consumption and device area increase
Solution Approach 1:
The patent merges the functions of memory read, computation, and threshold comparison into a single integrated operation. The same circuit paths used to read memristor values are also used to perform MAC operations and compare results against thresholds, eliminating the need for separate high-power comparator circuits and reducing overall power consumption
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed circuit enables efficient integration of binary neural networks with reduced bulkiness and improved integrability into memory cells, supporting larger neurons and parallel operations with robustness against cell variability.
Implementation Method 1
A memristor (or memristor) is a passive electronic component. The name is a portmanteau of the English words 'memory' and 'resistor.' A memristor is a non-volatile memory component; its electrical resistance changes when a voltage is applied for a certain duration and remains at that value when the voltage is removed.
Implementation Method 2
A weight of 1 is generally encoded by a low-resistance state, denoted LRS (from the English Low Resistance State), and a weight equal to 0 by a state of high resistance, denoted HRS (from the English High Resistance State). If the input value corresponding to a given weight is 1, then—according to Ohm's law—a current will flow through the cell carrying the weight, equal to the product of the input value and the weight value.
Implementation Method 3
The cells are connected via source lines, usually denoted SL (from English Source Line), the currents add up via Kirchhoff's law, resulting in a MAC operation (from the English Multiply And Accumulate) well known for neural network inference.
Data Source
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AI summary
This electronic circuit performs binary calculations and comprises word, bit, and source lines, and memory cells arranged in rows and columns. Cells in the same row are selectable by at least one word line, while those in the same column are connected to a pair of complementary bit lines and at least one source line. Each memory cell contains at least one pair of memristors and at least one pair of switches. Each memristor in a cell is connected to a switch and to the same source line during each calculation. Each pair of memristors stores a binary value. The switches are connected, for activation, to a word line and a pair of complementary bit lines, with both switches in a pair connected to the same word line.It includes a read module, used during each calculation operation and comprising: - a logic unit for each column, each comprising an input terminal connected to a source line to receive an input value, called the column value, the logic unit switching between low and high values, depending on a comparison of the column value with a switching threshold value; and - a modification unit, for at least one logic unit and depending on the calculation operation, of a difference between the column value and said threshold value.